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[AArch64][SVE] Asm: Support for reversed subtract (SUBR) instruction.

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This patch adds both a vector and an immediate form, e.g.                  
                                                                           
- Vector form:                                                             
                                                                           
    subr z0.h, p0/m, z0.h, z1.h                                            
                                                                           
  subtract active elements of z0 from z1, and store the result in z0.      
                                                                           
- Immediate form:                                                          
                                                                           
    subr z0.h, z0.h, #255                                                  
                                                                           
  subtract elements of z0, and store the result in z0.

llvm-svn: 336274
This commit is contained in:
Sander de Smalen 2018-07-04 14:05:33 +00:00
parent 141d1c9004
commit 561fb22163
3 changed files with 261 additions and 2 deletions
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6
lib/Target/AArch64/AArch64SVEInstrInfo.td
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@ -31,8 +31,9 @@ let Predicates = [HasSVE] in {
def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">;
defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">;
defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">;
@ -41,6 +42,7 @@ let Predicates = [HasSVE] in {
defm ADD_ZI : sve_int_arith_imm0<0b000, "add">;
defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">;
defm SUBR_ZI : sve_int_arith_imm0<0b011, "subr">;
defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">;
defm UQADD_ZI : sve_int_arith_imm0<0b101, "uqadd">;
defm SQSUB_ZI : sve_int_arith_imm0<0b110, "sqsub">;

140
test/MC/AArch64/SVE/subr-diagnostics.s Normal file
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@ -0,0 +1,140 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// Invalid element kind.
subr z0.h, p0/m, z0.h, z0.x
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
// CHECK-NEXT: subr z0.h, p0/m, z0.h, z0.x
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Element size specifiers should match.
subr z0.h, p0/m, z0.h, z0.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: subr z0.h, p0/m, z0.h, z0.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Invalid predicate suffix '/a'
subr z0.d, p7/a, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expecting 'm' or 'z' predication
// CHECK-NEXT: subr z0.d, p7/a, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix
subr z0.d, p7, z0.d, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: subr z0.d, p7, z0.d, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: restricted predicate has range [0, 7].
subr z26.b, p8/m, z26.b, z27.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: subr z26.b, p8/m, z26.b, z27.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z14.h, p8/m, z14.h, z18.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: subr z14.h, p8/m, z14.h, z18.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z30.s, p8/m, z30.s, z23.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: subr z30.s, p8/m, z30.s, z23.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z29.d, p8/m, z29.d, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: subr z29.d, p8/m, z29.d, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Source and Destination Registers must match
subr z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: subr z25.b, p4/m, z26.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z29.h, p6/m, z30.h, z20.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: subr z29.h, p6/m, z30.h, z20.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z14.s, p2/m, z15.s, z21.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: subr z14.s, p2/m, z15.s, z21.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z2.d, p5/m, z3.d, z11.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: subr z2.d, p5/m, z3.d, z11.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediates
subr z0.b, z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
// CHECK-NEXT: subr z0.b, z0.b, #0, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.b, z0.b, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
// CHECK-NEXT: subr z0.b, z0.b, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.b, z0.b, #1, lsl #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
// CHECK-NEXT: subr z0.b, z0.b, #1, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.b, z0.b, #256
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] with a shift amount of 0
// CHECK-NEXT: subr z0.b, z0.b, #256
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.h, z0.h, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.h, z0.h, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.h, z0.h, #256, lsl #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.h, z0.h, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.h, z0.h, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.h, z0.h, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.s, z0.s, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.s, z0.s, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.s, z0.s, #256, lsl #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.s, z0.s, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.s, z0.s, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.s, z0.s, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.d, z0.d, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.d, z0.d, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.d, z0.d, #256, lsl #8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.d, z0.d, #256, lsl #8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
subr z0.d, z0.d, #65536
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255] or a multiple of 256 in range [256, 65280]
// CHECK-NEXT: subr z0.d, z0.d, #65536
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

117
test/MC/AArch64/SVE/subr.s Normal file
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@ -0,0 +1,117 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
subr z0.b, p0/m, z0.b, z0.b
// CHECK-INST: subr z0.b, p0/m, z0.b, z0.b
// CHECK-ENCODING: [0x00,0x00,0x03,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 03 04 <unknown>
subr z0.h, p0/m, z0.h, z0.h
// CHECK-INST: subr z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0x43,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 43 04 <unknown>
subr z0.s, p0/m, z0.s, z0.s
// CHECK-INST: subr z0.s, p0/m, z0.s, z0.s
// CHECK-ENCODING: [0x00,0x00,0x83,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 83 04 <unknown>
subr z0.d, p0/m, z0.d, z0.d
// CHECK-INST: subr z0.d, p0/m, z0.d, z0.d
// CHECK-ENCODING: [0x00,0x00,0xc3,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 00 c3 04 <unknown>
subr z0.b, z0.b, #0
// CHECK-INST: subr z0.b, z0.b, #0
// CHECK-ENCODING: [0x00,0xc0,0x23,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 23 25 <unknown>
subr z31.b, z31.b, #255
// CHECK-INST: subr z31.b, z31.b, #255
// CHECK-ENCODING: [0xff,0xdf,0x23,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff df 23 25 <unknown>
subr z0.h, z0.h, #0
// CHECK-INST: subr z0.h, z0.h, #0
// CHECK-ENCODING: [0x00,0xc0,0x63,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 63 25 <unknown>
subr z0.h, z0.h, #0, lsl #8
// CHECK-INST: subr z0.h, z0.h, #0, lsl #8
// CHECK-ENCODING: [0x00,0xe0,0x63,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 e0 63 25 <unknown>
subr z31.h, z31.h, #255, lsl #8
// CHECK-INST: subr z31.h, z31.h, #65280
// CHECK-ENCODING: [0xff,0xff,0x63,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 63 25 <unknown>
subr z31.h, z31.h, #65280
// CHECK-INST: subr z31.h, z31.h, #65280
// CHECK-ENCODING: [0xff,0xff,0x63,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff 63 25 <unknown>
subr z0.s, z0.s, #0
// CHECK-INST: subr z0.s, z0.s, #0
// CHECK-ENCODING: [0x00,0xc0,0xa3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 a3 25 <unknown>
subr z0.s, z0.s, #0, lsl #8
// CHECK-INST: subr z0.s, z0.s, #0, lsl #8
// CHECK-ENCODING: [0x00,0xe0,0xa3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 e0 a3 25 <unknown>
subr z31.s, z31.s, #255, lsl #8
// CHECK-INST: subr z31.s, z31.s, #65280
// CHECK-ENCODING: [0xff,0xff,0xa3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff a3 25 <unknown>
subr z31.s, z31.s, #65280
// CHECK-INST: subr z31.s, z31.s, #65280
// CHECK-ENCODING: [0xff,0xff,0xa3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff a3 25 <unknown>
subr z0.d, z0.d, #0
// CHECK-INST: subr z0.d, z0.d, #0
// CHECK-ENCODING: [0x00,0xc0,0xe3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 c0 e3 25 <unknown>
subr z0.d, z0.d, #0, lsl #8
// CHECK-INST: subr z0.d, z0.d, #0, lsl #8
// CHECK-ENCODING: [0x00,0xe0,0xe3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 e0 e3 25 <unknown>
subr z31.d, z31.d, #255, lsl #8
// CHECK-INST: subr z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e3 25 <unknown>
subr z31.d, z31.d, #65280
// CHECK-INST: subr z31.d, z31.d, #65280
// CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff ff e3 25 <unknown>