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[SystemZ] Support remaining atomic instructions
Add assembler support for all atomic instructions that weren't already supported. Some of those could be used to implement codegen for 128-bit atomic operations, but this isn't done here yet. llvm-svn: 288526
This commit is contained in:
Ulrich Weigand
parent
3319b28944
commit
564945a3af
@ -833,6 +833,23 @@ class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{15-0} = BD2;
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}
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class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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field bits<48> SoftFail = 0;
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bits<4> R1;
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bits<16> BD2;
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bits<4> R3;
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bits<16> BD4;
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let Inst{47-40} = op;
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let Inst{39-36} = R1;
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let Inst{35-32} = R3;
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let Inst{31-16} = BD2;
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let Inst{15-0} = BD4;
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}
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class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSystemZ<6, outs, ins, asmstr, pattern> {
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field bits<48> Inst;
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@ -2872,6 +2889,12 @@ multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
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}
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}
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class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
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: InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
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mnemonic#"\t$R3, $BD1, $BD2", []> {
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let mayLoad = 1;
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}
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class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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TypedReg tr, bits<4> type>
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: InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
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@ -3611,6 +3634,12 @@ multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
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VR128:$V4, imm32zx4:$M5, 0)>;
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}
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class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
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RegisterOperand cls>
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: InstSSe<opcode, (outs),
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(ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
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mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
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class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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RegisterOperand cls, AddressingMode mode = bdaddr20only>
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: InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
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@ -1546,11 +1546,40 @@ def ATOMIC_CMP_SWAPW
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let hasNoSchedulingInfo = 1;
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}
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// Test and set.
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let mayLoad = 1, Defs = [CC] in
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def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>;
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// Compare and swap.
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let Defs = [CC] in {
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defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
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def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
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}
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// Compare double and swap.
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let Defs = [CC] in {
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defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>;
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def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, null_frag, GR128>;
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}
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// Compare and swap and store.
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let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in
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def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>;
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// Perform locked operation.
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let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in
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def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>;
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// Load/store pair from/to quadword.
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def LPQ : UnaryRXY<"lpq", 0xE38F, null_frag, GR128, 16>;
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def STPQ : StoreRXY<"stpq", 0xE38E, null_frag, GR128, 16>;
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// Load pair disjoint.
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let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
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def LPD : BinarySSF<"lpd", 0xC84, GR128>;
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def LPDG : BinarySSF<"lpdg", 0xC85, GR128>;
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}
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//===----------------------------------------------------------------------===//
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// Access registers
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//===----------------------------------------------------------------------===//
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@ -537,9 +537,31 @@ def : InstRW<[FXb, LSU, Lat5], (instregex "LAN(G)?$")>;
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def : InstRW<[FXb, LSU, Lat5], (instregex "LAO(G)?$")>;
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def : InstRW<[FXb, LSU, Lat5], (instregex "LAX(G)?$")>;
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// Test and set
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def : InstRW<[FXb, LSU, Lat5, EndGroup], (instregex "TS$")>;
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// Compare and swap
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def : InstRW<[FXa, FXb, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
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// Compare double and swap
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def : InstRW<[FXa, FXa, FXb, FXb, FXa, LSU, Lat10, GroupAlone],
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(instregex "CDS(Y)?$")>;
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def : InstRW<[FXa, FXa, FXb, FXb, LSU, FXb, FXb, LSU, LSU, Lat20, GroupAlone],
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(instregex "CDSG$")>;
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// Compare and swap and store
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def : InstRW<[FXa, Lat30, GroupAlone], (instregex "CSST$")>;
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// Perform locked operation
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
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// Load/store pair from/to quadword
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def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
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def : InstRW<[FXb, FXb, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
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// Load pair disjoint
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def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
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//===----------------------------------------------------------------------===//
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// Access registers
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//===----------------------------------------------------------------------===//
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@ -494,9 +494,31 @@ def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
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// Test and set
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def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
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// Compare and swap
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def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
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// Compare double and swap
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def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
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(instregex "CDS(Y)?$")>;
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def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
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(instregex "CDSG$")>;
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// Compare and swap and store
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def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
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// Perform locked operation
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
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// Load/store pair from/to quadword
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def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
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def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
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// Load pair disjoint
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def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
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//===----------------------------------------------------------------------===//
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// Access registers
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//===----------------------------------------------------------------------===//
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@ -506,9 +506,31 @@ def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
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// Test and set
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def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
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// Compare and swap
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
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// Compare double and swap
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def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
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(instregex "CDS(Y)?$")>;
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def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
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(instregex "CDSG$")>;
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// Compare and swap and store
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def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
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// Perform locked operation
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
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// Load/store pair from/to quadword
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def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
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def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
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// Load pair disjoint
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def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
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//===----------------------------------------------------------------------===//
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// Access registers
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//===----------------------------------------------------------------------===//
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@ -1342,6 +1342,96 @@
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# CHECK: cdlgbr %f15, 0, %r0, 1
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0xb3 0xa1 0x01 0xf0
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# CHECK: cds %r0, %r0, 0
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0xbb 0x00 0x00 0x00
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# CHECK: cds %r0, %r0, 4095
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0xbb 0x00 0x0f 0xff
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# CHECK: cds %r0, %r0, 0(%r1)
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0xbb 0x00 0x10 0x00
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# CHECK: cds %r0, %r0, 0(%r15)
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0xbb 0x00 0xf0 0x00
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# CHECK: cds %r0, %r0, 4095(%r1)
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0xbb 0x00 0x1f 0xff
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# CHECK: cds %r0, %r0, 4095(%r15)
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0xbb 0x00 0xff 0xff
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# CHECK: cds %r0, %r14, 0
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0xbb 0x0e 0x00 0x00
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# CHECK: cds %r14, %r0, 0
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0xbb 0xe0 0x00 0x00
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# CHECK: cdsg %r0, %r0, -524288
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0xeb 0x00 0x00 0x00 0x80 0x3e
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# CHECK: cdsg %r0, %r0, -1
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0xeb 0x00 0x0f 0xff 0xff 0x3e
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# CHECK: cdsg %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0x3e
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# CHECK: cdsg %r0, %r0, 1
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0xeb 0x00 0x00 0x01 0x00 0x3e
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# CHECK: cdsg %r0, %r0, 524287
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0xeb 0x00 0x0f 0xff 0x7f 0x3e
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# CHECK: cdsg %r0, %r0, 0(%r1)
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0xeb 0x00 0x10 0x00 0x00 0x3e
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# CHECK: cdsg %r0, %r0, 0(%r15)
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0xeb 0x00 0xf0 0x00 0x00 0x3e
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# CHECK: cdsg %r0, %r0, 524287(%r1)
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0xeb 0x00 0x1f 0xff 0x7f 0x3e
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# CHECK: cdsg %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0x3e
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# CHECK: cdsg %r0, %r14, 0
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0xeb 0x0e 0x00 0x00 0x00 0x3e
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# CHECK: cdsg %r14, %r0, 0
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0xeb 0xe0 0x00 0x00 0x00 0x3e
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# CHECK: cdsy %r0, %r0, -524288
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0xeb 0x00 0x00 0x00 0x80 0x31
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# CHECK: cdsy %r0, %r0, -1
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0xeb 0x00 0x0f 0xff 0xff 0x31
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# CHECK: cdsy %r0, %r0, 0
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0xeb 0x00 0x00 0x00 0x00 0x31
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# CHECK: cdsy %r0, %r0, 1
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0xeb 0x00 0x00 0x01 0x00 0x31
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# CHECK: cdsy %r0, %r0, 524287
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0xeb 0x00 0x0f 0xff 0x7f 0x31
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# CHECK: cdsy %r0, %r0, 0(%r1)
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0xeb 0x00 0x10 0x00 0x00 0x31
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# CHECK: cdsy %r0, %r0, 0(%r15)
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0xeb 0x00 0xf0 0x00 0x00 0x31
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# CHECK: cdsy %r0, %r0, 524287(%r1)
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0xeb 0x00 0x1f 0xff 0x7f 0x31
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# CHECK: cdsy %r0, %r0, 524287(%r15)
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0xeb 0x00 0xff 0xff 0x7f 0x31
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# CHECK: cdsy %r0, %r14, 0
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0xeb 0x0e 0x00 0x00 0x00 0x31
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# CHECK: cdsy %r14, %r0, 0
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0xeb 0xe0 0x00 0x00 0x00 0x31
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# CHECK: cebr %f0, %f0
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0xb3 0x09 0x00 0x00
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@ -3451,6 +3541,27 @@
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# CHECK: csy %r15, %r0, 0
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0xeb 0xf0 0x00 0x00 0x00 0x14
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# CHECK: csst 0, 0, %r0
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0xc8 0x02 0x00 0x00 0x00 0x00
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# CHECK: csst 0, 4095, %r2
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0xc8 0x22 0x00 0x00 0x0f 0xff
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# CHECK: csst 0, 0(%r1), %r2
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0xc8 0x22 0x00 0x00 0x10 0x00
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# CHECK: csst 0, 0(%r15), %r2
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0xc8 0x22 0x00 0x00 0xf0 0x00
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# CHECK: csst 0(%r1), 4095(%r15), %r2
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0xc8 0x22 0x10 0x00 0xff 0xff
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# CHECK: csst 0(%r1), 0(%r15), %r2
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0xc8 0x22 0x10 0x00 0xf0 0x00
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# CHECK: csst 4095(%r1), 0(%r15), %r2
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0xc8 0x22 0x1f 0xff 0xf0 0x00
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# CHECK: c %r0, 0
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0x59 0x00 0x00 0x00
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@ -6442,6 +6553,48 @@
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# CHECK: locgr %r11, %r3, 15
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0xb9 0xe2 0xf0 0xb3
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# CHECK: lpd %r0, 0, 0
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0xc8 0x04 0x00 0x00 0x00 0x00
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# CHECK: lpd %r2, 0, 4095
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0xc8 0x24 0x00 0x00 0x0f 0xff
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# CHECK: lpd %r2, 0, 0(%r1)
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0xc8 0x24 0x00 0x00 0x10 0x00
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# CHECK: lpd %r2, 0, 0(%r15)
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0xc8 0x24 0x00 0x00 0xf0 0x00
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# CHECK: lpd %r2, 0(%r1), 4095(%r15)
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0xc8 0x24 0x10 0x00 0xff 0xff
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# CHECK: lpd %r2, 0(%r1), 0(%r15)
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0xc8 0x24 0x10 0x00 0xf0 0x00
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# CHECK: lpd %r2, 4095(%r1), 0(%r15)
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0xc8 0x24 0x1f 0xff 0xf0 0x00
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# CHECK: lpdg %r0, 0, 0
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0xc8 0x05 0x00 0x00 0x00 0x00
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# CHECK: lpdg %r2, 0, 4095
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0xc8 0x25 0x00 0x00 0x0f 0xff
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# CHECK: lpdg %r2, 0, 0(%r1)
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0xc8 0x25 0x00 0x00 0x10 0x00
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# CHECK: lpdg %r2, 0, 0(%r15)
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0xc8 0x25 0x00 0x00 0xf0 0x00
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# CHECK: lpdg %r2, 0(%r1), 4095(%r15)
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0xc8 0x25 0x10 0x00 0xff 0xff
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# CHECK: lpdg %r2, 0(%r1), 0(%r15)
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0xc8 0x25 0x10 0x00 0xf0 0x00
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# CHECK: lpdg %r2, 4095(%r1), 0(%r15)
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0xc8 0x25 0x1f 0xff 0xf0 0x00
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# CHECK: lpdbr %f0, %f9
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0xb3 0x10 0x00 0x09
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@ -6502,6 +6655,36 @@
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# CHECK: lpr %r7, %r8
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0x10 0x78
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# CHECK: lpq %r0, -524288
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0xe3 0x00 0x00 0x00 0x80 0x8f
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# CHECK: lpq %r0, -1
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0xe3 0x00 0x0f 0xff 0xff 0x8f
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# CHECK: lpq %r0, 0
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0xe3 0x00 0x00 0x00 0x00 0x8f
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# CHECK: lpq %r0, 1
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0xe3 0x00 0x00 0x01 0x00 0x8f
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# CHECK: lpq %r0, 524287
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0xe3 0x00 0x0f 0xff 0x7f 0x8f
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# CHECK: lpq %r0, 0(%r1)
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0xe3 0x00 0x10 0x00 0x00 0x8f
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# CHECK: lpq %r0, 0(%r15)
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0xe3 0x00 0xf0 0x00 0x00 0x8f
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# CHECK: lpq %r0, 524287(%r1,%r15)
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0xe3 0x01 0xff 0xff 0x7f 0x8f
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# CHECK: lpq %r0, 524287(%r15,%r1)
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0xe3 0x0f 0x1f 0xff 0x7f 0x8f
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|
||||
# CHECK: lpq %r14, 0
|
||||
0xe3 0xe0 0x00 0x00 0x00 0x8f
|
||||
|
||||
# CHECK: lpxbr %f0, %f8
|
||||
0xb3 0x40 0x00 0x08
|
||||
|
||||
@ -8395,6 +8578,27 @@
|
||||
# CHECK: pfd 15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x36
|
||||
|
||||
# CHECK: plo %r0, 0, %r0, 0
|
||||
0xee 0x00 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: plo %r2, 0, %r4, 4095
|
||||
0xee 0x24 0x00 0x00 0x0f 0xff
|
||||
|
||||
# CHECK: plo %r2, 0, %r4, 0(%r1)
|
||||
0xee 0x24 0x00 0x00 0x10 0x00
|
||||
|
||||
# CHECK: plo %r2, 0, %r4, 0(%r15)
|
||||
0xee 0x24 0x00 0x00 0xf0 0x00
|
||||
|
||||
# CHECK: plo %r2, 0(%r1), %r4, 4095(%r15)
|
||||
0xee 0x24 0x10 0x00 0xff 0xff
|
||||
|
||||
# CHECK: plo %r2, 0(%r1), %r4, 0(%r15)
|
||||
0xee 0x24 0x10 0x00 0xf0 0x00
|
||||
|
||||
# CHECK: plo %r2, 4095(%r1), %r4, 0(%r15)
|
||||
0xee 0x24 0x1f 0xff 0xf0 0x00
|
||||
|
||||
# CHECK: pr
|
||||
0x01 0x01
|
||||
|
||||
@ -10528,6 +10732,36 @@
|
||||
# CHECK: stocg %r1, 2(%r3), 15
|
||||
0xeb 0x1f 0x30 0x02 0x00 0xe3
|
||||
|
||||
# CHECK: stpq %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x8e
|
||||
|
||||
# CHECK: stpq %r0, -1
|
||||
0xe3 0x00 0x0f 0xff 0xff 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 0
|
||||
0xe3 0x00 0x00 0x00 0x00 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 1
|
||||
0xe3 0x00 0x00 0x01 0x00 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 524287
|
||||
0xe3 0x00 0x0f 0xff 0x7f 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 0(%r1)
|
||||
0xe3 0x00 0x10 0x00 0x00 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 0(%r15)
|
||||
0xe3 0x00 0xf0 0x00 0x00 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 524287(%r1,%r15)
|
||||
0xe3 0x01 0xff 0xff 0x7f 0x8e
|
||||
|
||||
# CHECK: stpq %r0, 524287(%r15,%r1)
|
||||
0xe3 0x0f 0x1f 0xff 0x7f 0x8e
|
||||
|
||||
# CHECK: stpq %r14, 0
|
||||
0xe3 0xe0 0x00 0x00 0x00 0x8e
|
||||
|
||||
# CHECK: s %r0, 0
|
||||
0x5b 0x00 0x00 0x00
|
||||
|
||||
@ -10885,6 +11119,24 @@
|
||||
# CHECK: tmy 524287(%r15), 42
|
||||
0xeb 0x2a 0xff 0xff 0x7f 0x51
|
||||
|
||||
# CHECK: ts 0
|
||||
0x93 0x00 0x00 0x00
|
||||
|
||||
# CHECK: ts 0(%r1)
|
||||
0x93 0x00 0x10 0x00
|
||||
|
||||
#CHECK: ts 0(%r15)
|
||||
0x93 0x00 0xf0 0x00
|
||||
|
||||
#CHECK: ts 4095
|
||||
0x93 0x00 0x0f 0xff
|
||||
|
||||
#CHECK: ts 4095(%r1)
|
||||
0x93 0x00 0x1f 0xff
|
||||
|
||||
#CHECK: ts 4095(%r15)
|
||||
0x93 0x00 0xff 0xff
|
||||
|
||||
# CHECK: xc 0(1), 0
|
||||
0xd7 0x00 0x00 0x00 0x00 0x00
|
||||
|
||||
|
||||
@ -762,6 +762,46 @@
|
||||
|
||||
niai 0, 0
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: lpd %r1, 0, 0
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: lpd %r2, 160(%r1,%r15), 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpd %r2, -1(%r1), 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpd %r2, 4096(%r1), 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpd %r2, 0(%r1), -1(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpd %r2, 0(%r1), 4096(%r15)
|
||||
|
||||
lpd %r1, 0, 0
|
||||
lpd %r2, 160(%r1,%r15), 160(%r15)
|
||||
lpd %r2, -1(%r1), 160(%r15)
|
||||
lpd %r2, 4096(%r1), 160(%r15)
|
||||
lpd %r2, 0(%r1), -1(%r15)
|
||||
lpd %r2, 0(%r1), 4096(%r15)
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: lpdg %r1, 0, 0
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: lpdg %r2, 160(%r1,%r15), 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpdg %r2, -1(%r1), 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpdg %r2, 4096(%r1), 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpdg %r2, 0(%r1), -1(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpdg %r2, 0(%r1), 4096(%r15)
|
||||
|
||||
lpdg %r1, 0, 0
|
||||
lpdg %r2, 160(%r1,%r15), 160(%r15)
|
||||
lpdg %r2, -1(%r1), 160(%r15)
|
||||
lpdg %r2, 4096(%r1), 160(%r15)
|
||||
lpdg %r2, 0(%r1), -1(%r15)
|
||||
lpdg %r2, 0(%r1), 4096(%r15)
|
||||
|
||||
#CHECK: error: instruction requires: transactional-execution
|
||||
#CHECK: ntstg %r0, 524287(%r1,%r15)
|
||||
|
||||
|
||||
@ -553,6 +553,57 @@
|
||||
|
||||
cdlgbr %f0, 0, %r0, 0
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cds %r1, %r0, 0
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cds %r0, %r1, 0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: cds %r0, %r0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: cds %r0, %r0, 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: cds %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
cds %r1, %r0, 0
|
||||
cds %r0, %r1, 0
|
||||
cds %r0, %r0, -1
|
||||
cds %r0, %r0, 4096
|
||||
cds %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cdsg %r1, %r0, 0
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cdsg %r0, %r1, 0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: cdsg %r0, %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: cdsg %r0, %r0, 524288
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: cdsg %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
cdsg %r1, %r0, 0
|
||||
cdsg %r0, %r1, 0
|
||||
cdsg %r0, %r0, -524289
|
||||
cdsg %r0, %r0, 524288
|
||||
cdsg %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cdsy %r1, %r0, 0
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cdsy %r0, %r1, 0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: cdsy %r0, %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: cdsy %r0, %r0, 524288
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: cdsy %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
cdsy %r1, %r0, 0
|
||||
cdsy %r0, %r1, 0
|
||||
cdsy %r0, %r0, -524289
|
||||
cdsy %r0, %r0, 524288
|
||||
cdsy %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: ceb %f0, -1
|
||||
#CHECK: error: invalid operand
|
||||
@ -1482,6 +1533,23 @@
|
||||
csy %r0, %r0, 524288
|
||||
csy %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: csst 160(%r1,%r15), 160(%r15), %r2
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: csst -1(%r1), 160(%r15), %r2
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: csst 4096(%r1), 160(%r15), %r2
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: csst 0(%r1), -1(%r15), %r2
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: csst 0(%r1), 4096(%r15), %r2
|
||||
|
||||
csst 160(%r1,%r15), 160(%r15), %r2
|
||||
csst -1(%r1), 160(%r15), %r2
|
||||
csst 4096(%r1), 160(%r15), %r2
|
||||
csst 0(%r1), -1(%r15), %r2
|
||||
csst 0(%r1), 4096(%r15), %r2
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: cxbr %f0, %f2
|
||||
#CHECK: error: invalid register pair
|
||||
@ -2365,6 +2433,25 @@
|
||||
lnxbr %f0, %f2
|
||||
lnxbr %f2, %f0
|
||||
|
||||
#CHECK: error: instruction requires: interlocked-access1
|
||||
#CHECK: lpd %r0, 0, 0
|
||||
lpd %r0, 0, 0
|
||||
|
||||
#CHECK: error: instruction requires: interlocked-access1
|
||||
#CHECK: lpdg %r0, 0, 0
|
||||
lpdg %r0, 0, 0
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: lpq %r1, 0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpq %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lpq %r0, 524288
|
||||
|
||||
lpq %r1, 0
|
||||
lpq %r0, -524289
|
||||
lpq %r0, 524288
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: lpxbr %f0, %f2
|
||||
#CHECK: error: invalid register pair
|
||||
@ -3150,6 +3237,23 @@
|
||||
pfdrl 1, 1
|
||||
pfdrl 1, 0x100000000
|
||||
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: plo %r2, 160(%r1,%r15), %r4, 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: plo %r2, -1(%r1), %r4, 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: plo %r2, 4096(%r1), %r4, 160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: plo %r2, 0(%r1), %r4, -1(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: plo %r2, 0(%r1), %r4, 4096(%r15)
|
||||
|
||||
plo %r2, 160(%r1,%r15), %r4, 160(%r15)
|
||||
plo %r2, -1(%r1), %r4, 160(%r15)
|
||||
plo %r2, 4096(%r1), %r4, 160(%r15)
|
||||
plo %r2, 0(%r1), %r4, -1(%r15)
|
||||
plo %r2, 0(%r1), %r4, 4096(%r15)
|
||||
|
||||
#CHECK: error: instruction requires: population-count
|
||||
#CHECK: popcnt %r0, %r0
|
||||
|
||||
@ -3780,6 +3884,17 @@
|
||||
stmy %r0, %r0, 524288
|
||||
stmy %r0, %r0, 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid register pair
|
||||
#CHECK: stpq %r1, 0
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stpq %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stpq %r0, 524288
|
||||
|
||||
stpq %r1, 0
|
||||
stpq %r0, -524289
|
||||
stpq %r0, 524288
|
||||
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: strag 160(%r1,%r15),160(%r15)
|
||||
#CHECK: error: invalid operand
|
||||
@ -3957,6 +4072,17 @@
|
||||
tmy 0, -1
|
||||
tmy 0, 256
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: ts -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: ts 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: ts 0(%r1,%r2)
|
||||
|
||||
ts -1
|
||||
ts 4096
|
||||
ts 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: x %r0, -1
|
||||
#CHECK: error: invalid operand
|
||||
|
||||
@ -1227,6 +1227,34 @@
|
||||
locrnp %r1,%r3
|
||||
locrno %r1,%r3
|
||||
|
||||
#CHECK: lpd %r0, 0, 0 # encoding: [0xc8,0x04,0x00,0x00,0x00,0x00]
|
||||
#CHECK: lpd %r2, 0(%r1), 0(%r15) # encoding: [0xc8,0x24,0x10,0x00,0xf0,0x00]
|
||||
#CHECK: lpd %r2, 1(%r1), 0(%r15) # encoding: [0xc8,0x24,0x10,0x01,0xf0,0x00]
|
||||
#CHECK: lpd %r2, 4095(%r1), 0(%r15) # encoding: [0xc8,0x24,0x1f,0xff,0xf0,0x00]
|
||||
#CHECK: lpd %r2, 0(%r1), 1(%r15) # encoding: [0xc8,0x24,0x10,0x00,0xf0,0x01]
|
||||
#CHECK: lpd %r2, 0(%r1), 4095(%r15) # encoding: [0xc8,0x24,0x10,0x00,0xff,0xff]
|
||||
|
||||
lpd %r0, 0, 0
|
||||
lpd %r2, 0(%r1), 0(%r15)
|
||||
lpd %r2, 1(%r1), 0(%r15)
|
||||
lpd %r2, 4095(%r1), 0(%r15)
|
||||
lpd %r2, 0(%r1), 1(%r15)
|
||||
lpd %r2, 0(%r1), 4095(%r15)
|
||||
|
||||
#CHECK: lpdg %r0, 0, 0 # encoding: [0xc8,0x05,0x00,0x00,0x00,0x00]
|
||||
#CHECK: lpdg %r2, 0(%r1), 0(%r15) # encoding: [0xc8,0x25,0x10,0x00,0xf0,0x00]
|
||||
#CHECK: lpdg %r2, 1(%r1), 0(%r15) # encoding: [0xc8,0x25,0x10,0x01,0xf0,0x00]
|
||||
#CHECK: lpdg %r2, 4095(%r1), 0(%r15) # encoding: [0xc8,0x25,0x1f,0xff,0xf0,0x00]
|
||||
#CHECK: lpdg %r2, 0(%r1), 1(%r15) # encoding: [0xc8,0x25,0x10,0x00,0xf0,0x01]
|
||||
#CHECK: lpdg %r2, 0(%r1), 4095(%r15) # encoding: [0xc8,0x25,0x10,0x00,0xff,0xff]
|
||||
|
||||
lpdg %r0, 0, 0
|
||||
lpdg %r2, 0(%r1), 0(%r15)
|
||||
lpdg %r2, 1(%r1), 0(%r15)
|
||||
lpdg %r2, 4095(%r1), 0(%r15)
|
||||
lpdg %r2, 0(%r1), 1(%r15)
|
||||
lpdg %r2, 0(%r1), 4095(%r15)
|
||||
|
||||
#CHECK: ngrk %r0, %r0, %r0 # encoding: [0xb9,0xe4,0x00,0x00]
|
||||
#CHECK: ngrk %r0, %r0, %r15 # encoding: [0xb9,0xe4,0xf0,0x00]
|
||||
#CHECK: ngrk %r0, %r15, %r0 # encoding: [0xb9,0xe4,0x00,0x0f]
|
||||
|
||||
@ -1849,6 +1849,72 @@
|
||||
cdgbr %f7, %r8
|
||||
cdgbr %f15, %r15
|
||||
|
||||
#CHECK: cds %r0, %r0, 0 # encoding: [0xbb,0x00,0x00,0x00]
|
||||
#CHECK: cds %r0, %r0, 4095 # encoding: [0xbb,0x00,0x0f,0xff]
|
||||
#CHECK: cds %r0, %r0, 0(%r1) # encoding: [0xbb,0x00,0x10,0x00]
|
||||
#CHECK: cds %r0, %r0, 0(%r15) # encoding: [0xbb,0x00,0xf0,0x00]
|
||||
#CHECK: cds %r0, %r0, 4095(%r1) # encoding: [0xbb,0x00,0x1f,0xff]
|
||||
#CHECK: cds %r0, %r0, 4095(%r15) # encoding: [0xbb,0x00,0xff,0xff]
|
||||
#CHECK: cds %r0, %r14, 0 # encoding: [0xbb,0x0e,0x00,0x00]
|
||||
#CHECK: cds %r14, %r0, 0 # encoding: [0xbb,0xe0,0x00,0x00]
|
||||
|
||||
cds %r0, %r0, 0
|
||||
cds %r0, %r0, 4095
|
||||
cds %r0, %r0, 0(%r1)
|
||||
cds %r0, %r0, 0(%r15)
|
||||
cds %r0, %r0, 4095(%r1)
|
||||
cds %r0, %r0, 4095(%r15)
|
||||
cds %r0, %r14, 0
|
||||
cds %r14, %r0, 0
|
||||
|
||||
#CHECK: cdsg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x3e]
|
||||
#CHECK: cdsg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x3e]
|
||||
#CHECK: cdsg %r0, %r14, 0 # encoding: [0xeb,0x0e,0x00,0x00,0x00,0x3e]
|
||||
#CHECK: cdsg %r14, %r0, 0 # encoding: [0xeb,0xe0,0x00,0x00,0x00,0x3e]
|
||||
|
||||
cdsg %r0, %r0, -524288
|
||||
cdsg %r0, %r0, -1
|
||||
cdsg %r0, %r0, 0
|
||||
cdsg %r0, %r0, 1
|
||||
cdsg %r0, %r0, 524287
|
||||
cdsg %r0, %r0, 0(%r1)
|
||||
cdsg %r0, %r0, 0(%r15)
|
||||
cdsg %r0, %r0, 524287(%r1)
|
||||
cdsg %r0, %r0, 524287(%r15)
|
||||
cdsg %r0, %r14, 0
|
||||
cdsg %r14, %r0, 0
|
||||
|
||||
#CHECK: cdsy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x31]
|
||||
#CHECK: cdsy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x31]
|
||||
#CHECK: cdsy %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x31]
|
||||
#CHECK: cdsy %r0, %r14, 0 # encoding: [0xeb,0x0e,0x00,0x00,0x00,0x31]
|
||||
#CHECK: cdsy %r14, %r0, 0 # encoding: [0xeb,0xe0,0x00,0x00,0x00,0x31]
|
||||
|
||||
cdsy %r0, %r0, -524288
|
||||
cdsy %r0, %r0, -1
|
||||
cdsy %r0, %r0, 0
|
||||
cdsy %r0, %r0, 1
|
||||
cdsy %r0, %r0, 524287
|
||||
cdsy %r0, %r0, 0(%r1)
|
||||
cdsy %r0, %r0, 0(%r15)
|
||||
cdsy %r0, %r0, 524287(%r1)
|
||||
cdsy %r0, %r0, 524287(%r15)
|
||||
cdsy %r0, %r14, 0
|
||||
cdsy %r14, %r0, 0
|
||||
|
||||
#CHECK: ceb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x09]
|
||||
#CHECK: ceb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x09]
|
||||
#CHECK: ceb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x09]
|
||||
@ -5581,6 +5647,20 @@
|
||||
csy %r0, %r15, 0
|
||||
csy %r15, %r0, 0
|
||||
|
||||
#CHECK: csst 0, 0, %r0 # encoding: [0xc8,0x02,0x00,0x00,0x00,0x00]
|
||||
#CHECK: csst 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xf0,0x00]
|
||||
#CHECK: csst 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x01,0xf0,0x00]
|
||||
#CHECK: csst 4095(%r1), 0(%r15), %r2 # encoding: [0xc8,0x22,0x1f,0xff,0xf0,0x00]
|
||||
#CHECK: csst 0(%r1), 1(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xf0,0x01]
|
||||
#CHECK: csst 0(%r1), 4095(%r15), %r2 # encoding: [0xc8,0x22,0x10,0x00,0xff,0xff]
|
||||
|
||||
csst 0, 0, %r0
|
||||
csst 0(%r1), 0(%r15), %r2
|
||||
csst 1(%r1), 0(%r15), %r2
|
||||
csst 4095(%r1), 0(%r15), %r2
|
||||
csst 0(%r1), 1(%r15), %r2
|
||||
csst 0(%r1), 4095(%r15), %r2
|
||||
|
||||
#CHECK: cxbr %f0, %f0 # encoding: [0xb3,0x49,0x00,0x00]
|
||||
#CHECK: cxbr %f0, %f13 # encoding: [0xb3,0x49,0x00,0x0d]
|
||||
#CHECK: cxbr %f8, %f8 # encoding: [0xb3,0x49,0x00,0x88]
|
||||
@ -7516,6 +7596,28 @@
|
||||
lpgr %r15,%r0
|
||||
lpgr %r7,%r8
|
||||
|
||||
#CHECK: lpq %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x8f]
|
||||
#CHECK: lpq %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x8f]
|
||||
#CHECK: lpq %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x8f]
|
||||
#CHECK: lpq %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x8f]
|
||||
#CHECK: lpq %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x8f]
|
||||
#CHECK: lpq %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x8f]
|
||||
#CHECK: lpq %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x8f]
|
||||
#CHECK: lpq %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x8f]
|
||||
#CHECK: lpq %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x8f]
|
||||
#CHECK: lpq %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x8f]
|
||||
|
||||
lpq %r0, -524288
|
||||
lpq %r0, -1
|
||||
lpq %r0, 0
|
||||
lpq %r0, 1
|
||||
lpq %r0, 524287
|
||||
lpq %r0, 0(%r1)
|
||||
lpq %r0, 0(%r15)
|
||||
lpq %r0, 524287(%r1,%r15)
|
||||
lpq %r0, 524287(%r15,%r1)
|
||||
lpq %r14, 0
|
||||
|
||||
#CHECK: lpr %r0, %r0 # encoding: [0x10,0x00]
|
||||
#CHECK: lpr %r0, %r15 # encoding: [0x10,0x0f]
|
||||
#CHECK: lpr %r15, %r0 # encoding: [0x10,0xf0]
|
||||
@ -8982,6 +9084,20 @@
|
||||
pfdrl 7, frob@PLT
|
||||
pfdrl 8, frob@PLT
|
||||
|
||||
#CHECK: plo %r0, 0, %r0, 0 # encoding: [0xee,0x00,0x00,0x00,0x00,0x00]
|
||||
#CHECK: plo %r2, 0(%r1), %r4, 0(%r15) # encoding: [0xee,0x24,0x10,0x00,0xf0,0x00]
|
||||
#CHECK: plo %r2, 1(%r1), %r4, 0(%r15) # encoding: [0xee,0x24,0x10,0x01,0xf0,0x00]
|
||||
#CHECK: plo %r2, 4095(%r1), %r4, 0(%r15) # encoding: [0xee,0x24,0x1f,0xff,0xf0,0x00]
|
||||
#CHECK: plo %r2, 0(%r1), %r4, 1(%r15) # encoding: [0xee,0x24,0x10,0x00,0xf0,0x01]
|
||||
#CHECK: plo %r2, 0(%r1), %r4, 4095(%r15) # encoding: [0xee,0x24,0x10,0x00,0xff,0xff]
|
||||
|
||||
plo %r0, 0, %r0, 0
|
||||
plo %r2, 0(%r1), %r4, 0(%r15)
|
||||
plo %r2, 1(%r1), %r4, 0(%r15)
|
||||
plo %r2, 4095(%r1), %r4, 0(%r15)
|
||||
plo %r2, 0(%r1), %r4, 1(%r15)
|
||||
plo %r2, 0(%r1), %r4, 4095(%r15)
|
||||
|
||||
#CHECK: pr # encoding: [0x01,0x01]
|
||||
pr
|
||||
|
||||
@ -10257,6 +10373,28 @@
|
||||
stmy %r0,%r0,524287(%r1)
|
||||
stmy %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: stpq %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x8e]
|
||||
#CHECK: stpq %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x8e]
|
||||
#CHECK: stpq %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x8e]
|
||||
#CHECK: stpq %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x8e]
|
||||
#CHECK: stpq %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x8e]
|
||||
#CHECK: stpq %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x8e]
|
||||
#CHECK: stpq %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x8e]
|
||||
#CHECK: stpq %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x8e]
|
||||
#CHECK: stpq %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x8e]
|
||||
#CHECK: stpq %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x8e]
|
||||
|
||||
stpq %r0, -524288
|
||||
stpq %r0, -1
|
||||
stpq %r0, 0
|
||||
stpq %r0, 1
|
||||
stpq %r0, 524287
|
||||
stpq %r0, 0(%r1)
|
||||
stpq %r0, 0(%r15)
|
||||
stpq %r0, 524287(%r1,%r15)
|
||||
stpq %r0, 524287(%r15,%r1)
|
||||
stpq %r14, 0
|
||||
|
||||
#CHECK: strag 0, 0 # encoding: [0xe5,0x02,0x00,0x00,0x00,0x00]
|
||||
#CHECK: strag 0(%r1), 0(%r2) # encoding: [0xe5,0x02,0x10,0x00,0x20,0x00]
|
||||
#CHECK: strag 160(%r1), 320(%r15) # encoding: [0xe5,0x02,0x10,0xa0,0xf1,0x40]
|
||||
@ -10596,6 +10734,20 @@
|
||||
tmy 524287(%r1), 42
|
||||
tmy 524287(%r15), 42
|
||||
|
||||
#CHECK: ts 0 # encoding: [0x93,0x00,0x00,0x00]
|
||||
#CHECK: ts 0(%r1) # encoding: [0x93,0x00,0x10,0x00]
|
||||
#CHECK: ts 0(%r15) # encoding: [0x93,0x00,0xf0,0x00]
|
||||
#CHECK: ts 4095 # encoding: [0x93,0x00,0x0f,0xff]
|
||||
#CHECK: ts 4095(%r1) # encoding: [0x93,0x00,0x1f,0xff]
|
||||
#CHECK: ts 4095(%r15) # encoding: [0x93,0x00,0xff,0xff]
|
||||
|
||||
ts 0
|
||||
ts 0(%r1)
|
||||
ts 0(%r15)
|
||||
ts 4095
|
||||
ts 4095(%r1)
|
||||
ts 4095(%r15)
|
||||
|
||||
#CHECK: x %r0, 0 # encoding: [0x57,0x00,0x00,0x00]
|
||||
#CHECK: x %r0, 4095 # encoding: [0x57,0x00,0x0f,0xff]
|
||||
#CHECK: x %r0, 0(%r1) # encoding: [0x57,0x00,0x10,0x00]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user