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AMDGPU/GlobalISel: Make i32 xor legal
llvm-svn: 326466
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2869f6a9d5
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565e3b87de
@ -35,6 +35,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
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setAction({G_ADD, S32}, Legal);
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setAction({G_AND, S32}, Legal);
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setAction({G_OR, S32}, Legal);
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setAction({G_XOR, S32}, Legal);
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setAction({G_BITCAST, V2S16}, Legal);
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setAction({G_BITCAST, 1, S32}, Legal);
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@ -79,8 +81,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
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setAction({G_LOAD, 1, P1}, Legal);
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setAction({G_LOAD, 1, P2}, Legal);
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setAction({G_OR, S32}, Legal);
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setAction({G_SELECT, S32}, Legal);
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setAction({G_SELECT, 1, S1}, Legal);
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18
test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
Normal file
18
test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
Normal file
@ -0,0 +1,18 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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---
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name: test_xor
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: test_xor
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = G_XOR %0, %1
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$vgpr0 = COPY %2
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...
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