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https://github.com/RPCS3/llvm-mirror.git
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RegisterScavenging: Add ScavengerTest pass
This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
This commit is contained in:
Matthias Braun
parent
0531e97657
commit
5693b1e8e8
@ -330,6 +330,7 @@ void initializeSanitizerCoverageModulePass(PassRegistry&);
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void initializeScalarEvolutionWrapperPassPass(PassRegistry&);
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void initializeScalarizeMaskedMemIntrinPass(PassRegistry&);
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void initializeScalarizerPass(PassRegistry&);
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void initializeScavengerTestPass(PassRegistry&);
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void initializeScopedNoAliasAAWrapperPassPass(PassRegistry&);
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void initializeSeparateConstOffsetFromGEPPass(PassRegistry&);
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void initializeShadowStackGCLoweringPass(PassRegistry&);
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@ -15,19 +15,23 @@
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/PassSupport.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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@ -555,5 +559,37 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {
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}
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}
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MRI.clearVirtRegs();
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MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
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}
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namespace {
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/// This class runs register scavenging independ of the PrologEpilogInserter.
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/// This is used in for testing.
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class ScavengerTest : public MachineFunctionPass {
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public:
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static char ID;
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ScavengerTest() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) {
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const TargetSubtargetInfo &STI = MF.getSubtarget();
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const TargetFrameLowering &TFL = *STI.getFrameLowering();
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RegScavenger RS;
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// Let's hope that calling those outside of PrologEpilogueInserter works
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// well enough to initialize the scavenger with some emergency spillslots
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// for the target.
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BitVector SavedRegs;
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TFL.determineCalleeSaves(MF, SavedRegs, &RS);
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TFL.processFunctionBeforeFrameFinalized(MF, &RS);
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// Let's scavenge the current function
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scavengeFrameVirtualRegs(MF, RS);
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return true;
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}
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};
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char ScavengerTest::ID;
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} // end anonymous namespace
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INITIALIZE_PASS(ScavengerTest, "scavenger-test",
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"Scavenge virtual registers inside basic blocks", false, false)
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149
test/CodeGen/PowerPC/scavenging.mir
Normal file
149
test/CodeGen/PowerPC/scavenging.mir
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@ -0,0 +1,149 @@
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# RUN: llc -mtriple=ppc64-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s
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---
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# CHECK-LABEL: name: noscav0
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name: noscav0
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK: [[REG0:%r[0-9]+]] = LI 42
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; CHECK-NEXT: NOP implicit [[REG0]]
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%0 : gprc = LI 42
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NOP implicit %0
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; CHECK: [[REG1:%r[0-9]+]] = LI 42
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; CHECK-NEXT: NOP
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; CHECK-NEXT: NOP implicit [[REG1]]
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; CHECK-NEXT: NOP
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; CHECK-NEXT: NOP implicit [[REG1]]
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%1 : gprc = LI 42
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NOP
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NOP implicit %1
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NOP
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NOP implicit %1
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; CHECK: [[REG2:%r[0-9]+]] = LI 42
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; CHECK-NEXT: NOP implicit [[REG2]]
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%2 : gprc = LI 42
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NOP implicit %2
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%x0 = IMPLICIT_DEF
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%x1 = IMPLICIT_DEF
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%x2 = IMPLICIT_DEF
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%x3 = IMPLICIT_DEF
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%x4 = IMPLICIT_DEF
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%x27 = IMPLICIT_DEF
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%x28 = IMPLICIT_DEF
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%x29 = IMPLICIT_DEF
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%x30 = IMPLICIT_DEF
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; CHECK-NOT: %x0 = LI 42
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; CHECK-NOT: %x1 = LI 42
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; CHECK-NOT: %x2 = LI 42
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; CHECK-NOT: %x3 = LI 42
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; CHECK-NOT: %x4 = LI 42
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; CHECK-NOT: %x5 = LI 42
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; CHECK-NOT: %x27 = LI 42
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; CHECK-NOT: %x28 = LI 42
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; CHECK-NOT: %x29 = LI 42
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; CHECK-NOT: %x30 = LI 42
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; CHECK: [[REG3:%r[0-9]+]] = LI 42
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; CHECK-NEXT: %x5 = IMPLICIT_DEF
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; CHECK-NEXT: NOP implicit [[REG2]]
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; CHECK-NEXT: NOP implicit [[REG3]]
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%3 : gprc = LI 42
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%x5 = IMPLICIT_DEF
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NOP implicit %2
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NOP implicit %3
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NOP implicit %x0
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NOP implicit %x1
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NOP implicit %x2
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NOP implicit %x3
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NOP implicit %x4
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NOP implicit %x5
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NOP implicit %x27
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NOP implicit %x28
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NOP implicit %x29
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NOP implicit %x30
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...
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---
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# CHECK-LABEL: name: scav0
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name: scav0
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tracksRegLiveness: true
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stack:
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# variable-sized object should be a reason to reserve an emergency spillslot
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# in the RegScavenger
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- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
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body: |
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bb.0:
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%x0 = IMPLICIT_DEF
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%x1 = IMPLICIT_DEF
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%x2 = IMPLICIT_DEF
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%x3 = IMPLICIT_DEF
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%x4 = IMPLICIT_DEF
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%x5 = IMPLICIT_DEF
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%x6 = IMPLICIT_DEF
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%x7 = IMPLICIT_DEF
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%x8 = IMPLICIT_DEF
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%x9 = IMPLICIT_DEF
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%x10 = IMPLICIT_DEF
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%x11 = IMPLICIT_DEF
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%x12 = IMPLICIT_DEF
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%x13 = IMPLICIT_DEF
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%x14 = IMPLICIT_DEF
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%x15 = IMPLICIT_DEF
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%x16 = IMPLICIT_DEF
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%x17 = IMPLICIT_DEF
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%x18 = IMPLICIT_DEF
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%x19 = IMPLICIT_DEF
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%x20 = IMPLICIT_DEF
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%x21 = IMPLICIT_DEF
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%x22 = IMPLICIT_DEF
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%x23 = IMPLICIT_DEF
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%x24 = IMPLICIT_DEF
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%x25 = IMPLICIT_DEF
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%x26 = IMPLICIT_DEF
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%x27 = IMPLICIT_DEF
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%x28 = IMPLICIT_DEF
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%x29 = IMPLICIT_DEF
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%x30 = IMPLICIT_DEF
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; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]]
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; CHECK: [[SPILLEDREG]] = LI8 42
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; CHECK: NOP implicit [[SPILLEDREG]]
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; CHECK: [[SPILLEDREG]] = LD
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%0 : g8rc = LI8 42
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NOP implicit %0
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NOP implicit %x0
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NOP implicit %x1
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NOP implicit %x2
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NOP implicit %x3
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NOP implicit %x4
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NOP implicit %x5
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NOP implicit %x6
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NOP implicit %x7
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NOP implicit %x8
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NOP implicit %x9
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NOP implicit %x10
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NOP implicit %x11
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NOP implicit %x12
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NOP implicit %x13
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NOP implicit %x14
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NOP implicit %x15
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NOP implicit %x16
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NOP implicit %x17
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NOP implicit %x18
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NOP implicit %x19
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NOP implicit %x20
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NOP implicit %x21
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NOP implicit %x22
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NOP implicit %x23
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NOP implicit %x24
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NOP implicit %x25
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NOP implicit %x26
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NOP implicit %x27
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NOP implicit %x28
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NOP implicit %x29
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NOP implicit %x30
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...
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54
test/CodeGen/X86/scavenger.mir
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54
test/CodeGen/X86/scavenger.mir
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@ -0,0 +1,54 @@
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# RUN: llc -mtriple=i386-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s
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---
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# CHECK-LABEL: name: func0
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name: func0
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tracksRegLiveness: true
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body: |
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bb.0:
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%0 : gr32 = MOV32ri 42
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%ebp = COPY %0
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...
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---
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# CHECK-LABEL: name: func2
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-NOT: %eax = MOV32ri 42
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; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42
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; CHECK: %ebp = COPY [[REG0]]
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%eax = MOV32ri 13
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%0 : gr32 = MOV32ri 42
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%ebp = COPY %0
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; CHECK: [[REG1:%e[a-z]+]] = MOV32ri 23
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; CHECK: [[REG2:%e[a-z]+]] = MOV32ri 7
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; CHECK: [[REG1]] = ADD32ri8 [[REG1]], 5, implicit-def dead %eflags
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%1 : gr32 = MOV32ri 23
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%2 : gr32 = MOV32ri 7
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%1 = ADD32ri8 %1, 5, implicit-def dead %eflags
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NOOP implicit %ebp
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; CHECK: NOOP implicit [[REG2]]
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; CHECK: NOOP implicit [[REG1]]
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NOOP implicit %2
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NOOP implicit %1
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RETQ %eax
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...
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---
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# Defs without uses are currently broken
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#name: func3
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#tracksRegLiveness: true
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#body: |
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# bb.0:
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# dead %0 : gr32 = MOV32ri 42
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...
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---
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# Uses without defs are currently broken (and honestly not that useful).
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#name: func3
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#tracksRegLiveness: true
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#body: |
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# bb.0:
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# NOOP undef implicit %0 : gr32
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...
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@ -304,6 +304,9 @@ int main(int argc, char **argv) {
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initializeScalarizeMaskedMemIntrinPass(*Registry);
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initializeExpandReductionsPass(*Registry);
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// Initialize debugging passes.
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initializeScavengerTestPass(*Registry);
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// Register the target printer for --version.
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cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
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