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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183494
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d6271f8e18
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56998a5288
@ -71,8 +71,8 @@ void PPCScoreboardHazardRecognizer::Reset() {
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// 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
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// 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
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//
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//
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PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
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PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM)
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: TII(tii) {
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: TM(TM) {
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EndDispatchGroup();
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EndDispatchGroup();
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}
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}
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@ -91,7 +91,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
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bool &isFirst, bool &isSingle,
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bool &isFirst, bool &isSingle,
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bool &isCracked,
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bool &isCracked,
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bool &isLoad, bool &isStore) {
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bool &isLoad, bool &isStore) {
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const MCInstrDesc &MCID = TII.get(Opcode);
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const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode);
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isLoad = MCID.mayLoad();
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isLoad = MCID.mayLoad();
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isStore = MCID.mayStore();
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isStore = MCID.mayStore();
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@ -43,7 +43,7 @@ public:
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/// setting the CTR register then branching through it within a dispatch group),
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/// setting the CTR register then branching through it within a dispatch group),
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/// or storing then loading from the same address within a dispatch group.
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/// or storing then loading from the same address within a dispatch group.
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class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
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class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
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const TargetInstrInfo &TII;
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const TargetMachine &TM;
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unsigned NumIssued; // Number of insts issued, including advanced cycles.
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unsigned NumIssued; // Number of insts issued, including advanced cycles.
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@ -64,7 +64,7 @@ class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
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unsigned NumStores;
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unsigned NumStores;
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public:
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public:
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PPCHazardRecognizer970(const TargetInstrInfo &TII);
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PPCHazardRecognizer970(const TargetMachine &TM);
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual void EmitInstruction(SUnit *SU);
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void AdvanceCycle();
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@ -74,8 +74,6 @@ static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
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PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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: TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
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: TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
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const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
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const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
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PPCRegInfo = TM.getRegisterInfo();
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PPCII = TM.getInstrInfo();
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setPow2DivIsCheap();
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setPow2DivIsCheap();
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@ -6072,7 +6070,9 @@ PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
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// Setup
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// Setup
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MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
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MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
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MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
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const PPCRegisterInfo *TRI =
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static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
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MIB.addRegMask(TRI->getNoPreservedMask());
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BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
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BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
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@ -6235,8 +6235,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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Cond.push_back(MI->getOperand(1));
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Cond.push_back(MI->getOperand(1));
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DebugLoc dl = MI->getDebugLoc();
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DebugLoc dl = MI->getDebugLoc();
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PPCII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), Cond,
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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MI->getOperand(2).getReg(), MI->getOperand(3).getReg());
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TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
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Cond, MI->getOperand(2).getReg(),
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MI->getOperand(3).getReg());
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} else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
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} else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
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MI->getOpcode() == PPC::SELECT_CC_I8 ||
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MI->getOpcode() == PPC::SELECT_CC_I8 ||
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MI->getOpcode() == PPC::SELECT_CC_F4 ||
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MI->getOpcode() == PPC::SELECT_CC_F4 ||
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@ -335,8 +335,6 @@ namespace llvm {
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class PPCTargetLowering : public TargetLowering {
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class PPCTargetLowering : public TargetLowering {
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const PPCSubtarget &PPCSubTarget;
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const PPCSubtarget &PPCSubTarget;
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const PPCRegisterInfo *PPCRegInfo;
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const PPCInstrInfo *PPCII;
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public:
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public:
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explicit PPCTargetLowering(PPCTargetMachine &TM);
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explicit PPCTargetLowering(PPCTargetMachine &TM);
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@ -47,7 +47,7 @@ cl::desc("Disable compare instruction optimization"), cl::Hidden);
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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: PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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: PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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TM(tm), RI(*TM.getSubtargetImpl()) {}
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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/// this target when scheduling the DAG.
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@ -77,7 +77,7 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetInstrInfo *TII = TM.getInstrInfo();
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assert(TII && "No InstrInfo?");
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assert(TII && "No InstrInfo?");
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return new PPCHazardRecognizer970(*TII);
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return new PPCHazardRecognizer970(TM);
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}
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}
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return new PPCScoreboardHazardRecognizer(II, DAG);
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return new PPCScoreboardHazardRecognizer(II, DAG);
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@ -48,12 +48,11 @@
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using namespace llvm;
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using namespace llvm;
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
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const TargetInstrInfo &tii)
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: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
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: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
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ST.isPPC64() ? 0 : 1,
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ST.isPPC64() ? 0 : 1,
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ST.isPPC64() ? 0 : 1),
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ST.isPPC64() ? 0 : 1),
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Subtarget(ST), TII(tii) {
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Subtarget(ST) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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@ -219,6 +218,8 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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// Get the frame info.
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the instruction info.
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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// Determine whether 64-bit pointers are used.
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// Determine whether 64-bit pointers are used.
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bool LP64 = Subtarget.isPPC64();
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bool LP64 = Subtarget.isPPC64();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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@ -312,6 +313,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = Subtarget.isPPC64();
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bool LP64 = Subtarget.isPPC64();
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@ -355,6 +357,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = Subtarget.isPPC64();
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bool LP64 = Subtarget.isPPC64();
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@ -396,6 +399,7 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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@ -420,6 +424,7 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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DebugLoc dl = MI.getDebugLoc();
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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@ -497,6 +502,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock &MBB = *MI.getParent();
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// Get the basic block's function.
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// Get the basic block's function.
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB.getParent();
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// Get the instruction info.
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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// Get the frame info.
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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@ -706,9 +713,10 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB,
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if (Ins != MBB->end())
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if (Ins != MBB->end())
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DL = Ins->getDebugLoc();
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DL = Ins->getDebugLoc();
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const MachineFunction &MF = *MBB->getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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const MCInstrDesc &MCID = TII.get(ADDriOpc);
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const MCInstrDesc &MCID = TII.get(ADDriOpc);
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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const MachineFunction &MF = *MBB->getParent();
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MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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BuildMI(*MBB, Ins, DL, MCID, BaseReg)
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BuildMI(*MBB, Ins, DL, MCID, BaseReg)
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@ -29,9 +29,8 @@ class Type;
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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DenseMap<unsigned, unsigned> ImmToIdxMap;
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DenseMap<unsigned, unsigned> ImmToIdxMap;
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const PPCSubtarget &Subtarget;
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const PPCSubtarget &Subtarget;
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const TargetInstrInfo &TII;
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public:
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public:
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PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
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PPCRegisterInfo(const PPCSubtarget &SubTarget);
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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/// This is used for addressing modes.
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