mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
Added support for PIC code with "explicit relocations" *only*.
Removed all macro code for PIC (goodbye "la"). Support tested with shootout bench. llvm-svn: 43697
This commit is contained in:
Bruno Cardoso Lopes
parent
314e68f58f
commit
569b5512b0
@ -250,7 +250,7 @@ emitFunctionStart(MachineFunction &MF)
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emitMaskDirective(MF);
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emitFMaskDirective(MF);
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if (MF.getTarget().getRelocationModel() == Reloc::Static) {
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if (TM.getRelocationModel() == Reloc::Static) {
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emitSetDirective(NOREORDER);
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emitSetDirective(NOMACRO);
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}
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@ -262,7 +262,7 @@ emitFunctionStart(MachineFunction &MF)
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void MipsAsmPrinter::
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emitFunctionEnd(MachineFunction &MF)
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{
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if (MF.getTarget().getRelocationModel() == Reloc::Static) {
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if (TM.getRelocationModel() == Reloc::Static) {
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emitSetDirective(MACRO);
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emitSetDirective(REORDER);
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}
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@ -305,6 +305,9 @@ runOnMachineFunction(MachineFunction &MF)
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printInstruction(II);
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++EmittedInsts;
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}
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// Each Basic Block is separated by a newline
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O << '\n';
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}
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// Emit function end directives
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@ -319,17 +322,41 @@ printOperand(const MachineInstr *MI, int opNum)
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{
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const MachineOperand &MO = MI->getOperand(opNum);
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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bool closeP=false;
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bool closeP = false;
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bool isPIC = (TM.getRelocationModel() == Reloc::PIC_);
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bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
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// %hi and %lo used on mips gas to break large constants
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// %hi and %lo used on mips gas to load global addresses on
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// static code. %got is used to load global addresses when
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// using PIC_. %call16 is used to load direct call targets
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// on PIC_ and small code size. %call_lo and %call_hi load
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// direct call targets on PIC_ and large code size.
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if (MI->getOpcode() == Mips::LUi && !MO.isRegister()
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&& !MO.isImmediate()) {
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O << "%hi(";
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if ((isPIC) && (isCodeLarge))
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O << "%call_hi(";
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else
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O << "%hi(";
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closeP = true;
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} else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isRegister()
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&& !MO.isImmediate()) {
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O << "%lo(";
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closeP = true;
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} else if ((isPIC) && (MI->getOpcode() == Mips::LW)
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&& (!MO.isRegister()) && (!MO.isImmediate())) {
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const MachineOperand &firstMO = MI->getOperand(opNum-1);
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const MachineOperand &lastMO = MI->getOperand(opNum+1);
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if ((firstMO.isRegister()) && (lastMO.isRegister())) {
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if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() == Mips::GP)
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&& (!isCodeLarge))
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O << "%call16(";
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else if ((firstMO.getReg() != Mips::T9) && (lastMO.getReg() == Mips::GP))
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O << "%got(";
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else if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() != Mips::GP)
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&& (isCodeLarge))
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O << "%call_lo(";
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closeP = true;
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}
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}
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switch (MO.getType())
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@ -361,6 +388,7 @@ printOperand(const MachineInstr *MI, int opNum)
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O << MO.getSymbolName();
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break;
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// FIXME: Verify correct
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case MachineOperand::MO_ConstantPoolIndex:
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O << TAI->getPrivateGlobalPrefix() << "CPI"
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<< getFunctionNumber() << "_" << MO.getConstantPoolIndex();
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@ -385,7 +413,9 @@ printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier)
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return;
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}
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// Load/Store memory operands -- imm($reg)
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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printOperand(MI, opNum);
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O << "(";
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printOperand(MI, opNum+1);
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@ -15,6 +15,7 @@
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#include "Mips.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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@ -135,20 +136,24 @@ SelectAddr(SDOperand Op, SDOperand Addr, SDOperand &Offset, SDOperand &Base)
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return true;
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}
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// TargetExternalSymbol and TargetGlobalAddress are
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// lowered and their addresses go into registers, so
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// they should not be touched here.
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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// on PIC code Load GA
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if (Addr.getOpcode() == ISD::TargetGlobalAddress) {
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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Offset = Addr;
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return true;
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}
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} else {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD)
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{
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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{
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if (Predicate_immSExt16(CN))
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{
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_immSExt16(CN)) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0))) {
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@ -247,6 +252,51 @@ Select(SDOperand N)
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SDOperand MFInFlag = SDOperand(RemNode, 0);
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return CurDAG->getTargetNode(Mips::MFHI, MVT::i32, MFInFlag);
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}
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/// Handle direct and indirect calls when using PIC. On PIC, when
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/// GOT is smaller than about 64k (small code) the GA target is
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/// loaded with only one instruction. Otherwise GA's target must
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/// be loaded with 3 instructions.
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case MipsISD::JmpLink: {
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if (TM.getRelocationModel() == Reloc::PIC_) {
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//bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
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SDOperand Chain = Node->getOperand(0);
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SDOperand Callee = Node->getOperand(1);
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AddToISelQueue(Chain);
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SDOperand T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
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SDOperand InFlag(0, 0);
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if ( (isa<GlobalAddressSDNode>(Callee)) ||
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(isa<ExternalSymbolSDNode>(Callee)) )
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{
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/// Direct call for global addresses and external symbols
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SDOperand GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
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// Use load to get GOT target
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SDOperand Ops[] = { Callee, GPReg, Chain };
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SDOperand Load = SDOperand(CurDAG->getTargetNode(Mips::LW, MVT::i32,
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MVT::Other, Ops, 3), 0);
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Chain = Load.getValue(1);
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AddToISelQueue(Chain);
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// Call target must be on T9
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Chain = CurDAG->getCopyToReg(Chain, T9Reg, Load, InFlag);
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} else
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/// Indirect call
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Chain = CurDAG->getCopyToReg(Chain, T9Reg, Callee, InFlag);
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AddToISelQueue(Chain);
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// Emit Jump and Link Register
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SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, MVT::Other,
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MVT::Flag, T9Reg, Chain);
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Chain = SDOperand(ResNode, 0);
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InFlag = SDOperand(ResNode, 1);
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ReplaceUses(SDOperand(Node, 0), Chain);
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ReplaceUses(SDOperand(Node, 1), InFlag);
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return ResNode;
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}
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}
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}
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// Select the default instruction
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@ -39,13 +39,11 @@ getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode)
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{
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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case MipsISD::Add : return "MipsISD::Add";
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case MipsISD::LoadAddr : return "MipsISD::LoadAddr";
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default : return NULL;
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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default : return NULL;
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}
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}
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@ -149,21 +147,24 @@ LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
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{
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SDOperand ResNode;
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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bool isPIC = (getTargetMachine().getRelocationModel() == Reloc::PIC_);
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// On PIC code global addresses are loaded with "la" instruction
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if (!(getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
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SDOperand HiPart;
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if (!isPIC) {
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
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SDOperand Ops[] = { GA };
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HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
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} else // Emit Load from Global Pointer
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HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
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SDOperand Hi = DAG.getNode(MipsISD::Hi, VTs, 2, Ops, 1);
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SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
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// On functions and global targets not internal linked only
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// a load from got/GP is necessary for PIC to work.
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if ((isPIC) && ((!GV->hasInternalLinkage()) || (isa<Function>(GV))))
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return HiPart;
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SDOperand InFlag = Hi.getValue(1);
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ResNode = DAG.getNode(MipsISD::Add, MVT::i32, Lo, Hi, InFlag);
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} else
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ResNode = DAG.getNode(MipsISD::LoadAddr, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
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ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
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return ResNode;
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}
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@ -211,7 +212,7 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG)
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/// LowerCCCCallTo - functions arguments are copied from virtual
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/// regs to (physical regs)/(stack frame), CALLSEQ_START and
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/// CALLSEQ_END are emitted.
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/// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
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/// TODO: isVarArg, isTailCall, sret.
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SDOperand MipsTargetLowering::
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LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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{
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@ -244,7 +245,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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SmallVector<SDOperand, 8> MemOpChains;
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SDOperand StackPtr;
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unsigned LastStackLoc=0;
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int LastStackLoc=0;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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@ -268,8 +269,8 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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break;
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}
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// Arguments that can be passed on register,
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// must be kept at RegsToPass vector
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// Arguments that can be passed on register must be kept at
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// RegsToPass vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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@ -294,14 +295,6 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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}
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}
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// Create a stack location to hold GP when PIC is used
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MFI->CreateFixedObject(4, LastStackLoc);
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MipsFI->setGPStackOffset(LastStackLoc);
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}
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// Transform all store nodes into one single node because
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// all store nodes are independent of each other.
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if (!MemOpChains.empty())
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@ -321,13 +314,13 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it. Otherwise we have an indirect call,
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// if PIC is used, the call must use register GP
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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// node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
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else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
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// MipsJmpLink = #chain, #target_address, #opt_in_flags...
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// = Chain, Callee, Reg#1, Reg#2, ...
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//
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@ -349,6 +342,37 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Create a stack location to hold GP when PIC is used. This stack
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// location is used on function prologue to save GP and also after all
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// emited CALL's to restore GP.
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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// Function can have an arbitrary number of calls, so
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// hold the LastStackLoc with the biggest offset.
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int FI;
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (LastStackLoc >= MipsFI->getGPStackOffset()) {
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LastStackLoc = (!LastStackLoc) ? (16) : (LastStackLoc+4);
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// Create the frame index only once. SPOffset here can be anything
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// (this will be fixed on processFunctionBeforeFrameFinalized)
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if (MipsFI->getGPStackOffset() == -1) {
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FI = MFI->CreateFixedObject(4, 0);
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MipsFI->setGPFI(FI);
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}
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MipsFI->setGPStackOffset(LastStackLoc);
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}
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// Reload GP value.
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FI = MipsFI->getGPFI();
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SDOperand FIN = DAG.getFrameIndex(FI,getPointerTy());
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SDOperand GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
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Chain = GPLoad.getValue(1);
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Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
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GPLoad, SDOperand(0,0));
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}
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// Create the CALLSEQ_END node.
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NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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Ops.clear();
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@ -389,10 +413,11 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
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ResultVals.push_back(Chain.getValue(0));
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}
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// Merge everything together with a MERGE_VALUES node.
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ResultVals.push_back(Chain);
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// Merge everything together with a MERGE_VALUES node.
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return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
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&ResultVals[0], ResultVals.size()).Val;
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&ResultVals[0], ResultVals.size()).Val;
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}
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//===----------------------------------------------------------------------===//
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@ -38,13 +38,7 @@ namespace llvm {
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Lo,
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// Return
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Ret,
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// Need to support addition with a input flag
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Add,
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// Used on PIC Code to load global addresses
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LoadAddr
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Ret
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};
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}
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@ -22,20 +22,11 @@ def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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SDNPOutFlag]>;
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// Hi and Lo nodes are created to let easy manipulation of 16-bit when
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// handling 32-bit immediates. They are used on MipsISelLowering to
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// lower stuff like GlobalAddress, ExternalSymbol, ... on static model
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// This two nodes have nothing to do with Mips Registers Hi and Lo.
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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// Necessary to generate glued instructions when loading GlobalAddress
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// into registers.
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def MipsAdd : SDNode<"MipsISD::Add", SDTIntBinOp, [SDNPCommutative,
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SDNPAssociative, SDNPOptInFlag]>;
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// Used to Load Addresses on PIC code.
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def MipsLoadAddr: SDNode<"MipsISD::LoadAddr", SDTIntUnaryOp>;
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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// Return
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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@ -371,15 +362,9 @@ def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
|
||||
def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
|
||||
".set noreorder\n\t.cpload $reg\n\t.set reorder", []>;
|
||||
".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>;
|
||||
def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
|
||||
".cprestore $loc", []>;
|
||||
|
||||
// Used on PIC code only, it loads the address of label into register reg. The
|
||||
// address is calculated from the global pointer ($gp) and is expanded by the
|
||||
// assembler into two instructions "lw" and "addiu".
|
||||
def LA: PseudoInstMips<(outs CPURegs:$dst), (ins addrlabel:$label),
|
||||
"la $dst, $label", []>;
|
||||
".cprestore $loc\n", []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction definition
|
||||
@ -393,17 +378,13 @@ def LA: PseudoInstMips<(outs CPURegs:$dst), (ins addrlabel:$label),
|
||||
|
||||
// ADDiu just accept 16-bit immediates but we handle this on Pat's.
|
||||
// immZExt32 is used here so it can match GlobalAddress immediates.
|
||||
def ADDiu : ArithI<0x09, "addiu", MipsAdd, uimm16, immZExt16>;
|
||||
def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
|
||||
def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
|
||||
def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
|
||||
def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
|
||||
def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
|
||||
def ADD : ArithOverflowR<0x00, 0x20, "add">;
|
||||
def SUB : ArithOverflowR<0x00, 0x22, "sub">;
|
||||
def MADD : MArithR<0x00, "madd">;
|
||||
def MADDU : MArithR<0x01, "maddu">;
|
||||
def MSUB : MArithR<0x04, "msub">;
|
||||
def MSUBU : MArithR<0x05, "msubu">;
|
||||
|
||||
// Logical
|
||||
def AND : LogicR<0x24, "and", and>;
|
||||
@ -481,10 +462,16 @@ def MTLO : MoveFromTo<0x13, "mtlo">;
|
||||
// Count Leading
|
||||
// CLO/CLZ are part of the newer MIPS32(tm) instruction
|
||||
// set and not older Mips I keep this for future use
|
||||
// though.
|
||||
// though.
|
||||
//def CLO : CountLeading<0x21, "clo">;
|
||||
//def CLZ : CountLeading<0x20, "clz">;
|
||||
|
||||
// MADD*/MSUB* are not part of MipsI either.
|
||||
//def MADD : MArithR<0x00, "madd">;
|
||||
//def MADDU : MArithR<0x01, "maddu">;
|
||||
//def MSUB : MArithR<0x04, "msub">;
|
||||
//def MSUBU : MArithR<0x05, "msubu">;
|
||||
|
||||
// No operation
|
||||
let addr=0 in
|
||||
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
|
||||
@ -529,9 +516,8 @@ def : Pat<(MipsJmpLink CPURegs:$dst),
|
||||
// GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
|
||||
def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
||||
def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
||||
def : Pat<(MipsAdd CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
||||
def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
||||
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
||||
def : Pat<(MipsLoadAddr tglobaladdr:$in), (LA tglobaladdr:$in)>;
|
||||
|
||||
// Mips does not have not, so we increase the operation
|
||||
def : Pat<(not CPURegs:$in),
|
||||
@ -544,6 +530,9 @@ def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
|
||||
def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
|
||||
(SB CPURegs:$src, addr:$addr)>;
|
||||
|
||||
// some peepholes
|
||||
def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
||||
|
||||
///
|
||||
/// brcond patterns
|
||||
///
|
||||
|
||||
@ -33,11 +33,6 @@ private:
|
||||
/// the Return Address must be saved
|
||||
int RAStackOffset;
|
||||
|
||||
/// When PIC is used the GP must be saved on the stack
|
||||
/// on the function prologue, so a reference to its stack
|
||||
/// location must be kept.
|
||||
int GPStackOffset;
|
||||
|
||||
/// MipsFIHolder - Holds a FrameIndex and it's Stack Pointer Offset
|
||||
struct MipsFIHolder {
|
||||
|
||||
@ -48,6 +43,13 @@ private:
|
||||
: FI(FrameIndex), SPOffset(StackPointerOffset) {}
|
||||
};
|
||||
|
||||
/// When PIC is used the GP must be saved on the stack
|
||||
/// on the function prologue and must be reloaded from this
|
||||
/// stack location after every call. A reference to its stack
|
||||
/// location and frame index must be kept to be used on
|
||||
/// emitPrologue and processFunctionBeforeFrameFinalized.
|
||||
MipsFIHolder GPHolder;
|
||||
|
||||
// On LowerFORMAL_ARGUMENTS the stack size is unknown,
|
||||
// so the Stack Pointer Offset calculation of "not in
|
||||
// register arguments" must be postponed to emitPrologue.
|
||||
@ -64,7 +66,7 @@ private:
|
||||
|
||||
public:
|
||||
MipsFunctionInfo(MachineFunction& MF)
|
||||
: FPStackOffset(0), RAStackOffset(0),
|
||||
: FPStackOffset(0), RAStackOffset(0), GPHolder(-1,-1),
|
||||
HasLoadArgs(false), HasStoreVarArgs(false)
|
||||
{}
|
||||
|
||||
@ -74,8 +76,10 @@ public:
|
||||
int getRAStackOffset() const { return RAStackOffset; }
|
||||
void setRAStackOffset(int Off) { RAStackOffset = Off; }
|
||||
|
||||
int getGPStackOffset() const { return GPStackOffset; }
|
||||
void setGPStackOffset(int Off) { GPStackOffset = Off; }
|
||||
int getGPStackOffset() const { return GPHolder.SPOffset; }
|
||||
int getGPFI() const { return GPHolder.FI; }
|
||||
void setGPStackOffset(int Off) { GPHolder.SPOffset = Off; }
|
||||
void setGPFI(int FI) { GPHolder.FI = FI; }
|
||||
|
||||
int getTopSavedRegOffset() const {
|
||||
return (RAStackOffset > FPStackOffset) ?
|
||||
|
||||
@ -203,6 +203,12 @@ foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
|
||||
return NewMI;
|
||||
}
|
||||
|
||||
MachineInstr *MipsRegisterInfo::
|
||||
foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
|
||||
MachineInstr* LoadMI) const {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Callee Saved Registers methods
|
||||
@ -325,7 +331,7 @@ void MipsRegisterInfo::
|
||||
eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
RegScavenger *RS) const
|
||||
{
|
||||
MachineInstr &MI = *II;
|
||||
MachineInstr &MI = *II;
|
||||
MachineFunction &MF = *MI.getParent()->getParent();
|
||||
|
||||
unsigned i = 0;
|
||||
@ -359,7 +365,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
#endif
|
||||
|
||||
MI.getOperand(i-1).ChangeToImmediate(Offset);
|
||||
MI.getOperand(i).ChangeToRegister(getFrameRegister(MF),false);
|
||||
MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
|
||||
}
|
||||
|
||||
void MipsRegisterInfo::
|
||||
@ -453,7 +459,6 @@ emitPrologue(MachineFunction &MF) const
|
||||
if ((isPIC) && (MFI->hasCalls()))
|
||||
BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
|
||||
.addImm(MipsFI->getGPStackOffset());
|
||||
|
||||
}
|
||||
|
||||
void MipsRegisterInfo::
|
||||
@ -498,6 +503,17 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
|
||||
|
||||
void MipsRegisterInfo::
|
||||
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
|
||||
// Set the SPOffset on the FI where GP must be saved/loaded.
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
if (MFI->hasCalls()) {
|
||||
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
||||
#ifndef NDEBUG
|
||||
DOUT << "processFunctionBeforeFrameFinalized\n";
|
||||
DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
|
||||
DOUT << "FI :" << MipsFI->getGPFI() << "\n";
|
||||
#endif
|
||||
MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
|
||||
}
|
||||
}
|
||||
|
||||
unsigned MipsRegisterInfo::
|
||||
|
||||
@ -59,9 +59,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||
int FrameIndex) const;
|
||||
|
||||
MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
|
||||
MachineInstr* LoadMI) const {
|
||||
return 0;
|
||||
}
|
||||
MachineInstr* LoadMI) const;
|
||||
|
||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
|
||||
@ -35,6 +35,9 @@ createTargetAsmInfo() const
|
||||
// On function prologue, the stack is created by decrementing
|
||||
// its pointer. Once decremented, all references are done with positive
|
||||
// offset from the stack/frame pointer, so StackGrowsUp is used.
|
||||
// When using CodeModel::Large the behaviour
|
||||
//
|
||||
//
|
||||
MipsTargetMachine::
|
||||
MipsTargetMachine(const Module &M, const std::string &FS):
|
||||
Subtarget(*this, M, FS), DataLayout("E-p:32:32:32"),
|
||||
@ -43,6 +46,8 @@ MipsTargetMachine(const Module &M, const std::string &FS):
|
||||
{
|
||||
if (getRelocationModel() != Reloc::Static)
|
||||
setRelocationModel(Reloc::PIC_);
|
||||
if (getCodeModel() == CodeModel::Default)
|
||||
setCodeModel(CodeModel::Small);
|
||||
}
|
||||
|
||||
// return 0 and must specify -march to gen MIPS code.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user