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[AVR] Factor out mayLoad in tablegen patterns

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Patch by Gergo Erdi.

llvm-svn: 314897
This commit is contained in:
Dylan McKay 2017-10-04 10:36:07 +00:00
parent 9862729490
commit 569e524df6
1 changed files with 2 additions and 2 deletions
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4
lib/Target/AVR/AVRInstrInfo.td
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@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
// Load program memory operations.
let canFoldAsLoad = 1,
isReMaterializable = 1,
mayLoad = 1,
hasSideEffects = 0 in
{
let Defs = [R0],
@ -1437,8 +1438,7 @@ hasSideEffects = 0 in
Requires<[HasLPMX]>;
// Load program memory, while postincrementing the Z register.
let mayLoad = 1,
Defs = [R31R30] in
let Defs = [R31R30] in
{
def LPMRdZPi : FLPMX<0,
1,