RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 20:12:56 +02:00
Code Issues Projects Releases Wiki Activity

The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer.

Browse Source 
I've added the "zeroinitializer" case in this patch.

llvm-svn: 163506
This commit is contained in:
Elena Demikhovsky 2012-09-10 12:13:11 +00:00
parent 37ce5fbc3b
commit 56cdc6a59a
2 changed files with 38 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6030,14 +6030,25 @@ SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1);
DebugLoc dl = SVOp->getDebugLoc();
ArrayRef<int> MaskVals = SVOp->getMask();
SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
if (VT != MVT::v32i8 || !TLI.getSubtarget()->hasAVX2() || !V2IsUndef)
// VPSHUFB may be generated if
// (1) one of input vector is undefined or zeroinitializer.
// The mask value 0x80 puts 0 in the corresponding slot of the vector.
// And (2) the mask indexes don't cross the 128-bit lane.
if (VT != MVT::v32i8 || !TLI.getSubtarget()->hasAVX2() ||
(!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
return SDValue();
SmallVector<SDValue,32> pshufbMask;
if (V1IsAllZero && !V2IsAllZero) {
CommuteVectorShuffleMask(MaskVals, 32);
V1 = V2;
}
SmallVector<SDValue, 32> pshufbMask;
for (unsigned i = 0; i != 32; i++) {
int EltIdx = MaskVals[i];
if (EltIdx < 0 || EltIdx >= 32)

25
test/CodeGen/X86/avx2-shuffle.ll
View File

@ -36,4 +36,27 @@ define <32 x i8> @vpshufb_test(<32 x i8> %a) nounwind {
i32 18, i32 19, i32 30, i32 16, i32 25, i32 23, i32 17, i32 25,
i32 20, i32 19, i32 31, i32 17, i32 23, i32 undef, i32 29, i32 18>
ret <32 x i8>%S
}
}
; CHECK: vpshufb1_test
; CHECK; vpshufb {{.*\(%r.*}}, %ymm
; CHECK: ret
define <32 x i8> @vpshufb1_test(<32 x i8> %a) nounwind {
%S = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15,
i32 1, i32 9, i32 36, i32 11, i32 5, i32 13, i32 7, i32 15,
i32 18, i32 49, i32 30, i32 16, i32 25, i32 23, i32 17, i32 25,
i32 20, i32 19, i32 31, i32 17, i32 23, i32 undef, i32 29, i32 18>
ret <32 x i8>%S
}
; CHECK: vpshufb2_test
; CHECK; vpshufb {{.*\(%r.*}}, %ymm
; CHECK: ret
define <32 x i8> @vpshufb2_test(<32 x i8> %a) nounwind {
%S = shufflevector <32 x i8> zeroinitializer, <32 x i8> %a, <32 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15,
i32 1, i32 9, i32 36, i32 11, i32 5, i32 13, i32 7, i32 15,
i32 18, i32 49, i32 30, i32 16, i32 25, i32 23, i32 17, i32 25,
i32 20, i32 19, i32 31, i32 17, i32 23, i32 undef, i32 29, i32 18>
ret <32 x i8>%S
}