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AMDGPU: Also track whether SGPRs were spilled
llvm-svn: 252145
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4ca30f88e9
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@ -484,6 +484,8 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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int Opcode = -1;
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if (RI.isSGPRClass(RC)) {
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MFI->setHasSpilledSGPRs();
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// We are only allowed to create one new instruction when spilling
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// registers, so we need to use pseudo instruction for spilling
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// SGPRs.
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@ -29,6 +29,7 @@ void SIMachineFunctionInfo::anchor() {}
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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TIDReg(AMDGPU::NoRegister),
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HasSpilledSGPRs(false),
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HasSpilledVGPRs(false),
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PSInputAddr(0),
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NumUserSGPRs(0),
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@ -29,6 +29,7 @@ class SIMachineFunctionInfo : public AMDGPUMachineFunction {
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void anchor() override;
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unsigned TIDReg;
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bool HasSpilledSGPRs;
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bool HasSpilledVGPRs;
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public:
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@ -54,8 +55,22 @@ public:
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bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
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unsigned getTIDReg() const { return TIDReg; };
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void setTIDReg(unsigned Reg) { TIDReg = Reg; }
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bool hasSpilledVGPRs() const { return HasSpilledVGPRs; }
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void setHasSpilledVGPRs(bool Spill = true) { HasSpilledVGPRs = Spill; }
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bool hasSpilledSGPRs() const {
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return HasSpilledSGPRs;
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}
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void setHasSpilledSGPRs(bool Spill = true) {
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HasSpilledSGPRs = Spill;
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}
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bool hasSpilledVGPRs() const {
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return HasSpilledVGPRs;
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}
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void setHasSpilledVGPRs(bool Spill = true) {
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HasSpilledVGPRs = Spill;
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}
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unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
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};
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