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[AArch64][GlobalISel] Merge selection of vector-vector G_ASHR/G_LSHR and support more cases.
The vector-immediate cases are handled elsewhere in an earlier commit.
This commit is contained in:
Amara Emerson
parent
eaf34219d1
commit
56e14355d6
@ -18,6 +18,7 @@
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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@ -108,7 +109,7 @@ private:
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bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
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MachineRegisterInfo &MRI) const;
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bool selectVectorASHR(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
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// Helper to generate an equivalent of scalar_to_vector into a new register,
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@ -1511,9 +1512,10 @@ bool AArch64InstructionSelector::selectVectorSHL(
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return true;
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}
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bool AArch64InstructionSelector::selectVectorASHR(
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bool AArch64InstructionSelector::selectVectorAshrLshr(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_ASHR);
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assert(I.getOpcode() == TargetOpcode::G_ASHR ||
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I.getOpcode() == TargetOpcode::G_LSHR);
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Register DstReg = I.getOperand(0).getReg();
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const LLT Ty = MRI.getType(DstReg);
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Register Src1Reg = I.getOperand(1).getReg();
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@ -1522,25 +1524,34 @@ bool AArch64InstructionSelector::selectVectorASHR(
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if (!Ty.isVector())
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return false;
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bool IsASHR = I.getOpcode() == TargetOpcode::G_ASHR;
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// We expect the immediate case to be lowered in the PostLegalCombiner to
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// AArch64ISD::VASHR or AArch64ISD::VLSHR equivalents.
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// There is not a shift right register instruction, but the shift left
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// register instruction takes a signed value, where negative numbers specify a
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// right shift.
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unsigned Opc = 0;
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unsigned NegOpc = 0;
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const TargetRegisterClass *RC = nullptr;
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const TargetRegisterClass *RC =
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getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI);
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if (Ty == LLT::vector(2, 64)) {
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Opc = AArch64::SSHLv2i64;
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Opc = IsASHR ? AArch64::SSHLv2i64 : AArch64::USHLv2i64;
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NegOpc = AArch64::NEGv2i64;
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RC = &AArch64::FPR128RegClass;
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} else if (Ty == LLT::vector(4, 32)) {
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Opc = AArch64::SSHLv4i32;
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Opc = IsASHR ? AArch64::SSHLv4i32 : AArch64::USHLv4i32;
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NegOpc = AArch64::NEGv4i32;
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RC = &AArch64::FPR128RegClass;
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} else if (Ty == LLT::vector(2, 32)) {
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Opc = AArch64::SSHLv2i32;
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Opc = IsASHR ? AArch64::SSHLv2i32 : AArch64::USHLv2i32;
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NegOpc = AArch64::NEGv2i32;
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RC = &AArch64::FPR64RegClass;
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} else if (Ty == LLT::vector(4, 16)) {
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Opc = IsASHR ? AArch64::SSHLv4i16 : AArch64::USHLv4i16;
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NegOpc = AArch64::NEGv4i16;
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} else if (Ty == LLT::vector(8, 16)) {
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Opc = IsASHR ? AArch64::SSHLv8i16 : AArch64::USHLv8i16;
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NegOpc = AArch64::NEGv8i16;
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} else {
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LLVM_DEBUG(dbgs() << "Unhandled G_ASHR type");
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return false;
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@ -2452,22 +2463,21 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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// operands to use appropriate classes.
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_ASHR:
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if (MRI.getType(I.getOperand(0).getReg()).isVector())
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return selectVectorASHR(I, MRI);
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return selectVectorAshrLshr(I, MRI);
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_SHL:
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if (Opcode == TargetOpcode::G_SHL &&
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MRI.getType(I.getOperand(0).getReg()).isVector())
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return selectVectorSHL(I, MRI);
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_OR:
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case TargetOpcode::G_LSHR: {
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_OR: {
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// Reject the various things we don't support yet.
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if (unsupportedBinOp(I, RBI, MRI, TRI))
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return false;
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@ -322,7 +322,7 @@ body: |
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...
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---
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name: ashr_v4i64
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name: ashr_v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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@ -336,7 +336,7 @@ body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: ashr_v4i64
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; CHECK-LABEL: name: ashr_v2i64
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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@ -373,6 +373,102 @@ body: |
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RET_ReallyLR implicit $d0
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...
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---
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name: lshr_v4i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: lshr_v4i16
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]]
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; CHECK: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[NEGv4i16_]]
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; CHECK: $d0 = COPY [[USHLv4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = COPY $d1
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%2:fpr(<4 x s16>) = G_LSHR %0, %1(<4 x s16>)
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: lshr_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: lshr_v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]
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; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[NEGv4i32_]]
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; CHECK: $q0 = COPY [[USHLv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_LSHR %0, %1(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: lshr_v8i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: lshr_v8i16
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[NEGv8i16_:%[0-9]+]]:fpr128 = NEGv8i16 [[COPY1]]
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; CHECK: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[NEGv8i16_]]
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; CHECK: $q0 = COPY [[USHLv8i16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = COPY $q1
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%2:fpr(<8 x s16>) = G_LSHR %0, %1(<8 x s16>)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: ashr_v4i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: ashr_v4i16
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]]
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; CHECK: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY]], [[NEGv4i16_]]
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; CHECK: $d0 = COPY [[SSHLv4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = COPY $d1
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%2:fpr(<4 x s16>) = G_ASHR %0, %1(<4 x s16>)
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$d0 = COPY %2(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: vashr_v4i16_imm
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legalized: true
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regBankSelected: true
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