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* Added X86 store patterns.

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* Added X86 dec patterns.

llvm-svn: 24654
This commit is contained in:
Evan Cheng 2005-12-10 00:48:20 +00:00
parent 0b7a482921
commit 56f62789d7
3 changed files with 24 additions and 43 deletions
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5
lib/Target/TargetSelectionDAG.td
View File

@ -137,6 +137,10 @@ def SDTLoad : SDTypeProfile<1, 1, [ // load
SDTCisPtrTy<1>
]>;
def SDTStore : SDTypeProfile<0, 2, [ // store
SDTCisInt<1>
]>;
//===----------------------------------------------------------------------===//
// Selection DAG Node Properties.
//
@ -227,6 +231,7 @@ def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
//===----------------------------------------------------------------------===//
// Selection DAG Condition Codes

33
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -387,39 +387,6 @@ SDOperand X86DAGToDAGISel::Select(SDOperand Op) {
getI16Imm(X86Lowering.getBytesToPopOnReturn()),
Chain);
}
case ISD::STORE: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
SDOperand Tmp1 = Select(N->getOperand(1));
Opc = 0;
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
switch (CN->getValueType(0)) {
default: assert(0 && "Invalid type for operation!");
case MVT::i1:
case MVT::i8: Opc = X86::MOV8mi; break;
case MVT::i16: Opc = X86::MOV16mi; break;
case MVT::i32: Opc = X86::MOV32mi; break;
}
}
if (!Opc) {
switch (N->getOperand(1).getValueType()) {
default: assert(0 && "Cannot store this type!");
case MVT::i1:
case MVT::i8: Opc = X86::MOV8mr; break;
case MVT::i16: Opc = X86::MOV16mr; break;
case MVT::i32: Opc = X86::MOV32mr; break;
case MVT::f32: Opc = X86::MOVSSmr; break;
case MVT::f64: Opc = X86::FST64m; break;
}
}
SDOperand Base, Scale, Index, Disp;
SelectAddr(N->getOperand(2), Base, Scale, Index, Disp);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
Base, Scale, Index, Disp, Tmp1, Chain)
.getValue(Op.ResNo);
}
}
return SelectCode(Op);

29
lib/Target/X86/X86InstrInfo.td
View File

@ -378,11 +378,14 @@ def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
"mov{l} {$src, $dst|$dst, $src}",
[(set R32:$dst, imm:$src)]>;
def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}", []>;
"mov{b} {$src, $dst|$dst, $src}",
[(store (i8 imm:$src), addr:$dst)]>;
def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
"mov{w} {$src, $dst|$dst, $src}",
[(store (i16 imm:$src), addr:$dst)]>, OpSize;
def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
"mov{l} {$src, $dst|$dst, $src}", []>;
"mov{l} {$src, $dst|$dst, $src}",
[(store (i32 imm:$src), addr:$dst)]>;
def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
"mov{b} {$src, $dst|$dst, $src}",
@ -395,11 +398,14 @@ def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
[(set R32:$dst, (load addr:$src))]>;
def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
"mov{b} {$src, $dst|$dst, $src}", []>;
"mov{b} {$src, $dst|$dst, $src}",
[(store R8:$src, addr:$dst)]>;
def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
"mov{w} {$src, $dst|$dst, $src}",
[(store R16:$src, addr:$dst)]>, OpSize;
def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
"mov{l} {$src, $dst|$dst, $src}", []>;
"mov{l} {$src, $dst|$dst, $src}",
[(store R32:$src, addr:$dst)]>;
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...
@ -687,6 +693,7 @@ let isTwoAddress = 0 in {
def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst", []>;
}
// TODO: inc/dec is slow for P4, but fast for Pentium-M.
def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst",
[(set R8:$dst, (add R8:$src, 1))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
@ -701,11 +708,13 @@ let isTwoAddress = 0 in {
def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst", []>;
}
def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst", []>;
def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst",
[(set R8:$dst, (add R8:$src, -1))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst", []>,
OpSize;
def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst", []>;
def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst",
[(set R16:$dst, (add R16:$src, -1))]>, OpSize;
def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst",
[(set R32:$dst, (add R32:$src, -1))]>;
}
let isTwoAddress = 0 in {