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AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as

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it is set by CP

Differential Revision: https://reviews.llvm.org/D47392

llvm-svn: 333451
This commit is contained in:
Konstantin Zhuravlyov 2018-05-29 19:09:13 +00:00
parent 7618648e0d
commit 56fe8b5762
3 changed files with 10 additions and 13 deletions
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16
docs/AMDGPUUsage.rst
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@ -1858,17 +1858,13 @@ CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
Used by CP to set up Used by CP to set up
``COMPUTE_PGM_RSRC2.USER_SGPR``. ``COMPUTE_PGM_RSRC2.USER_SGPR``.
6 1 bit ENABLE_TRAP_HANDLER Set to 1 if code contains a 6 1 bit ENABLE_TRAP_HANDLER Must be 0.
TRAP instruction which
requires a trap handler to
be enabled.
CP sets This bit represents
``COMPUTE_PGM_RSRC2.TRAP_PRESENT`` ``COMPUTE_PGM_RSRC2.TRAP_PRESENT``,
if the runtime has which is set by the CP if
installed a trap handler the runtime has installed a
regardless of the setting trap handler.
of this field.
7 1 bit ENABLE_SGPR_WORKGROUP_ID_X Enable the setup of the 7 1 bit ENABLE_SGPR_WORKGROUP_ID_X Enable the setup of the
system SGPR register for system SGPR register for
the work-group id in the X the work-group id in the X

3
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
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@ -907,7 +907,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
ProgInfo.ComputePGMRSrc2 = ProgInfo.ComputePGMRSrc2 =
S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) | S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) | S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) | // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) | S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) | S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) | S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |

4
test/CodeGen/AMDGPU/trap.ll
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@ -26,7 +26,7 @@ declare void @llvm.debugtrap() #1
; NOMESA-TRAP-NEXT: .long 144 ; NOMESA-TRAP-NEXT: .long 144
; GCN-LABEL: {{^}}hsa_trap: ; GCN-LABEL: {{^}}hsa_trap:
; HSA-TRAP: enable_trap_handler = 1 ; HSA-TRAP: enable_trap_handler = 0
; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
; HSA-TRAP: s_trap 2 ; HSA-TRAP: s_trap 2
@ -56,7 +56,7 @@ define amdgpu_kernel void @hsa_trap(i32 addrspace(1)* nocapture readonly %arg0)
; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported ; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported
; GCN-LABEL: {{^}}hsa_debugtrap: ; GCN-LABEL: {{^}}hsa_debugtrap:
; HSA-TRAP: enable_trap_handler = 1 ; HSA-TRAP: enable_trap_handler = 0
; HSA-TRAP: s_trap 3 ; HSA-TRAP: s_trap 3
; HSA-TRAP: flat_store_dword v[0:1], v3 ; HSA-TRAP: flat_store_dword v[0:1], v3