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https://github.com/RPCS3/llvm-mirror.git
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[mips] Split expandLoadImmReal into multiple methods. NFC
The `expandLoadImmReal` handles four different and almost non-overlapping cases: loading a "single" float immediate into a GPR, loading a "single" float immediate into a FPR, and the same couple for a "double" float immediate. It's better to move each `else if` branch into separate methods. llvm-svn: 374164
This commit is contained in:
Simon Atanasyan
parent
b508b3b70b
commit
5708280dc2
@ -234,9 +234,14 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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MCStreamer &Out, const MCSubtargetInfo *STI);
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bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU,
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SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
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MCStreamer &Out, const MCSubtargetInfo *STI);
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bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
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const MCOperand &Offset, bool Is32BitAddress,
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@ -2455,25 +2460,21 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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: MER_Success;
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case Mips::LoadImmSingleGPR:
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return expandLoadImmReal(Inst, true, true, false, IDLoc, Out, STI)
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? MER_Fail
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: MER_Success;
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return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail
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: MER_Success;
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case Mips::LoadImmSingleFGR:
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return expandLoadImmReal(Inst, true, false, false, IDLoc, Out, STI)
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? MER_Fail
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: MER_Success;
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return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail
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: MER_Success;
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case Mips::LoadImmDoubleGPR:
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return expandLoadImmReal(Inst, false, true, false, IDLoc, Out, STI)
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? MER_Fail
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: MER_Success;
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return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail
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: MER_Success;
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case Mips::LoadImmDoubleFGR:
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return expandLoadImmReal(Inst, false, false, true, IDLoc, Out, STI)
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? MER_Fail
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: MER_Success;
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return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail
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: MER_Success;
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case Mips::LoadImmDoubleFGR_32:
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return expandLoadImmReal(Inst, false, false, false, IDLoc, Out, STI)
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? MER_Fail
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: MER_Success;
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return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail
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: MER_Success;
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case Mips::Ulh:
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return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::Ulhu:
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@ -3293,10 +3294,45 @@ bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
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return false;
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}
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bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR,
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bool Is64FPU, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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static uint64_t convertIntToDoubleImm(uint64_t ImmOp64) {
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// If ImmOp64 is AsmToken::Integer type (all bits set to zero in the
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// exponent field), convert it to double (e.g. 1 to 1.0)
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if ((Hi_32(ImmOp64) & 0x7ff00000) == 0) {
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APFloat RealVal(APFloat::IEEEdouble(), ImmOp64);
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ImmOp64 = RealVal.bitcastToAPInt().getZExtValue();
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}
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return ImmOp64;
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}
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static uint32_t covertDoubleImmToSingleImm(uint64_t ImmOp64) {
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// Conversion of a double in an uint64_t to a float in a uint32_t,
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// retaining the bit pattern of a float.
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double DoubleImm = BitsToDouble(ImmOp64);
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float TmpFloat = static_cast<float>(DoubleImm);
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return FloatToBits(TmpFloat);
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}
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bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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assert(Inst.getNumOperands() == 2 && "Invalid operand count");
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assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
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"Invalid instruction operand.");
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unsigned FirstReg = Inst.getOperand(0).getReg();
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uint64_t ImmOp64 = Inst.getOperand(1).getImm();
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ImmOp64 = convertIntToDoubleImm(ImmOp64);
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uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);
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return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc,
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Out, STI);
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}
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bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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assert(Inst.getNumOperands() == 2 && "Invalid operand count");
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assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
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@ -3305,166 +3341,181 @@ bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR,
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unsigned FirstReg = Inst.getOperand(0).getReg();
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uint64_t ImmOp64 = Inst.getOperand(1).getImm();
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uint32_t HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
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// If ImmOp64 is AsmToken::Integer type (all bits set to zero in the
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// exponent field), convert it to double (e.g. 1 to 1.0)
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if ((HiImmOp64 & 0x7ff00000) == 0) {
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APFloat RealVal(APFloat::IEEEdouble(), ImmOp64);
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ImmOp64 = RealVal.bitcastToAPInt().getZExtValue();
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}
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ImmOp64 = convertIntToDoubleImm(ImmOp64);
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uint32_t LoImmOp64 = ImmOp64 & 0xffffffff;
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HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
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uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);
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if (IsSingle) {
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// Conversion of a double in an uint64_t to a float in a uint32_t,
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// retaining the bit pattern of a float.
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uint32_t ImmOp32;
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double doubleImm = BitsToDouble(ImmOp64);
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float tmp_float = static_cast<float>(doubleImm);
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ImmOp32 = FloatToBits(tmp_float);
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if (IsGPR) {
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if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc,
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Out, STI))
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return true;
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return false;
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} else {
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unsigned ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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if (LoImmOp64 == 0) {
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if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc,
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Out, STI))
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return true;
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TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);
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return false;
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}
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MCSection *CS = getStreamer().getCurrentSectionOnly();
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// FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
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// where appropriate.
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MCSection *ReadOnlySection = getContext().getELFSection(
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".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
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MCSymbol *Sym = getContext().createTempSymbol();
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const MCExpr *LoSym =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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const MipsMCExpr *LoExpr =
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MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
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getStreamer().SwitchSection(ReadOnlySection);
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getStreamer().EmitLabel(Sym, IDLoc);
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getStreamer().EmitIntValue(ImmOp32, 4);
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getStreamer().SwitchSection(CS);
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if(emitPartialAddress(TOut, IDLoc, Sym))
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return true;
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TOut.emitRRX(Mips::LWC1, FirstReg, ATReg,
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MCOperand::createExpr(LoExpr), IDLoc, STI);
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}
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return false;
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}
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// if(!IsSingle)
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unsigned ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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if (IsGPR) {
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if (LoImmOp64 == 0) {
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if(isABI_N32() || isABI_N64()) {
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if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true,
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IDLoc, Out, STI))
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return true;
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return false;
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} else {
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if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,
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IDLoc, Out, STI))
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return true;
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if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true,
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IDLoc, Out, STI))
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return true;
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return false;
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}
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}
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MCSection *CS = getStreamer().getCurrentSectionOnly();
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MCSection *ReadOnlySection = getContext().getELFSection(
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".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
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MCSymbol *Sym = getContext().createTempSymbol();
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const MCExpr *LoSym =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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const MipsMCExpr *LoExpr =
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MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
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getStreamer().SwitchSection(ReadOnlySection);
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getStreamer().EmitLabel(Sym, IDLoc);
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getStreamer().EmitIntValue(HiImmOp64, 4);
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getStreamer().EmitIntValue(LoImmOp64, 4);
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getStreamer().SwitchSection(CS);
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if(emitPartialAddress(TOut, IDLoc, Sym))
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if (Lo_32(ImmOp64) == 0) {
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if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc, Out,
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STI))
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return true;
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if(isABI_N64())
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TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
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MCOperand::createExpr(LoExpr), IDLoc, STI);
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else
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TOut.emitRRX(Mips::ADDiu, ATReg, ATReg,
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MCOperand::createExpr(LoExpr), IDLoc, STI);
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TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);
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return false;
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}
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if(isABI_N32() || isABI_N64())
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TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI);
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else {
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TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI);
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TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI);
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MCSection *CS = getStreamer().getCurrentSectionOnly();
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// FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
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// where appropriate.
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MCSection *ReadOnlySection =
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getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
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MCSymbol *Sym = getContext().createTempSymbol();
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const MCExpr *LoSym =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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const MipsMCExpr *LoExpr =
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MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
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getStreamer().SwitchSection(ReadOnlySection);
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getStreamer().EmitLabel(Sym, IDLoc);
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getStreamer().EmitIntValue(ImmOp32, 4);
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getStreamer().SwitchSection(CS);
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if (emitPartialAddress(TOut, IDLoc, Sym))
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return true;
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TOut.emitRRX(Mips::LWC1, FirstReg, ATReg, MCOperand::createExpr(LoExpr),
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IDLoc, STI);
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return false;
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}
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bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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assert(Inst.getNumOperands() == 2 && "Invalid operand count");
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assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
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"Invalid instruction operand.");
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unsigned FirstReg = Inst.getOperand(0).getReg();
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uint64_t ImmOp64 = Inst.getOperand(1).getImm();
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ImmOp64 = convertIntToDoubleImm(ImmOp64);
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uint32_t LoImmOp64 = Lo_32(ImmOp64);
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uint32_t HiImmOp64 = Hi_32(ImmOp64);
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unsigned ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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if (LoImmOp64 == 0) {
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if (isABI_N32() || isABI_N64()) {
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if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true,
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IDLoc, Out, STI))
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return true;
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} else {
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if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,
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IDLoc, Out, STI))
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return true;
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if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true,
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IDLoc, Out, STI))
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return true;
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}
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return false;
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} else { // if(!IsGPR && !IsSingle)
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if ((LoImmOp64 == 0) &&
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!((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
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// FIXME: In the case where the constant is zero, we can load the
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// register directly from the zero register.
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if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc,
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Out, STI))
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return true;
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if (isABI_N32() || isABI_N64())
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TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI);
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else if (hasMips32r2()) {
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TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
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TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);
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} else {
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TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI);
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TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
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}
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return false;
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}
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MCSection *CS = getStreamer().getCurrentSectionOnly();
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// FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
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// where appropriate.
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MCSection *ReadOnlySection = getContext().getELFSection(
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".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
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MCSymbol *Sym = getContext().createTempSymbol();
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const MCExpr *LoSym =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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const MipsMCExpr *LoExpr =
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MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
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getStreamer().SwitchSection(ReadOnlySection);
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getStreamer().EmitLabel(Sym, IDLoc);
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getStreamer().EmitIntValue(HiImmOp64, 4);
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getStreamer().EmitIntValue(LoImmOp64, 4);
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getStreamer().SwitchSection(CS);
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if(emitPartialAddress(TOut, IDLoc, Sym))
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return true;
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TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg,
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MCOperand::createExpr(LoExpr), IDLoc, STI);
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}
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MCSection *CS = getStreamer().getCurrentSectionOnly();
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MCSection *ReadOnlySection =
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getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
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MCSymbol *Sym = getContext().createTempSymbol();
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const MCExpr *LoSym =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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const MipsMCExpr *LoExpr =
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MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
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getStreamer().SwitchSection(ReadOnlySection);
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getStreamer().EmitLabel(Sym, IDLoc);
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getStreamer().EmitIntValue(HiImmOp64, 4);
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getStreamer().EmitIntValue(LoImmOp64, 4);
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getStreamer().SwitchSection(CS);
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if (emitPartialAddress(TOut, IDLoc, Sym))
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return true;
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if (isABI_N64())
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TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
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IDLoc, STI);
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else
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TOut.emitRRX(Mips::ADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
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IDLoc, STI);
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if (isABI_N32() || isABI_N64())
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TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI);
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else {
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TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI);
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TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI);
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}
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return false;
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}
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bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
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SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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assert(Inst.getNumOperands() == 2 && "Invalid operand count");
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assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
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"Invalid instruction operand.");
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unsigned FirstReg = Inst.getOperand(0).getReg();
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uint64_t ImmOp64 = Inst.getOperand(1).getImm();
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ImmOp64 = convertIntToDoubleImm(ImmOp64);
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uint32_t LoImmOp64 = Lo_32(ImmOp64);
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uint32_t HiImmOp64 = Hi_32(ImmOp64);
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unsigned ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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if ((LoImmOp64 == 0) &&
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!((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
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// FIXME: In the case where the constant is zero, we can load the
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||||
// register directly from the zero register.
|
||||
if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc,
|
||||
Out, STI))
|
||||
return true;
|
||||
if (isABI_N32() || isABI_N64())
|
||||
TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI);
|
||||
else if (hasMips32r2()) {
|
||||
TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
|
||||
TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);
|
||||
} else {
|
||||
TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI);
|
||||
TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
MCSection *CS = getStreamer().getCurrentSectionOnly();
|
||||
// FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
|
||||
// where appropriate.
|
||||
MCSection *ReadOnlySection =
|
||||
getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
|
||||
|
||||
MCSymbol *Sym = getContext().createTempSymbol();
|
||||
const MCExpr *LoSym =
|
||||
MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
|
||||
const MipsMCExpr *LoExpr =
|
||||
MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
|
||||
|
||||
getStreamer().SwitchSection(ReadOnlySection);
|
||||
getStreamer().EmitLabel(Sym, IDLoc);
|
||||
getStreamer().EmitIntValue(HiImmOp64, 4);
|
||||
getStreamer().EmitIntValue(LoImmOp64, 4);
|
||||
getStreamer().SwitchSection(CS);
|
||||
|
||||
if (emitPartialAddress(TOut, IDLoc, Sym))
|
||||
return true;
|
||||
|
||||
TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg,
|
||||
MCOperand::createExpr(LoExpr), IDLoc, STI);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user