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https://github.com/RPCS3/llvm-mirror.git
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Revert r214881 because it broke lots of build-bots
llvm-svn: 214893
This commit is contained in:
Jonathan Roelofs
parent
1f56d11869
commit
5721e98d43
@ -2113,10 +2113,6 @@ ARMTargetLowering::LowerReturn(SDValue Chain,
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RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
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bool isLittleEndian = Subtarget->isLittle();
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MachineFunction &MF = DAG.getMachineFunction();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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AFI->setReturnRegsCount(RVLocs.size());
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// Copy the result values into the output registers.
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for (unsigned i = 0, realRVLocIdx = 0;
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i != RVLocs.size();
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@ -48,9 +48,6 @@ class ARMFunctionInfo : public MachineFunctionInfo {
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///
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unsigned ArgRegsSaveSize;
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/// ReturnRegsCount - Number of registers used up in the return.
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unsigned ReturnRegsCount;
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/// HasStackFrame - True if this function has a stack frame. Set by
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/// processFunctionBeforeCalleeSavedScan().
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bool HasStackFrame;
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@ -130,8 +127,7 @@ public:
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ARMFunctionInfo() :
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isThumb(false),
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hasThumb2(false),
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ArgRegsSaveSize(0), ReturnRegsCount(0), HasStackFrame(false),
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RestoreSPFromFP(false),
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ArgRegsSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false),
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LRSpilledForFarJump(false),
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FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
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GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
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@ -155,9 +151,6 @@ public:
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}
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void setArgRegsSaveSize(unsigned s) { ArgRegsSaveSize = s; }
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unsigned getReturnRegsCount() const { return ReturnRegsCount; }
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void setReturnRegsCount(unsigned s) { ReturnRegsCount = s; }
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bool hasStackFrame() const { return HasStackFrame; }
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void setHasStackFrame(bool s) { HasStackFrame = s; }
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@ -388,65 +388,28 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
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}
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}
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bool IsV4PopReturn = false;
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for (const CalleeSavedInfo &CSI : MFI->getCalleeSavedInfo())
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if (CSI.getReg() == ARM::LR)
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IsV4PopReturn = true;
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IsV4PopReturn &= STI.hasV4TOps() && !STI.hasV5TOps();
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if (ArgRegsSaveSize) {
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// Unlike T2 and ARM mode, the T1 pop instruction cannot restore
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// to LR, and we can't pop the value directly to the PC since
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// we need to update the SP after popping the value. So instead
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// we have to emit:
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// POP {r3}
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// ADD sp, #offset
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// BX r3
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// If this would clobber a return value, then generate this sequence instead:
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// MOV ip, r3
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// POP {r3}
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// ADD sp, #offset
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// MOV lr, r3
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// MOV r3, ip
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// BX lr
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if (ArgRegsSaveSize || IsV4PopReturn) {
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// we need to update the SP after popping the value. Therefore, we
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// pop the old LR into R3 as a temporary.
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// Get the last instruction, tBX_RET
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MBBI = MBB.getLastNonDebugInstr();
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assert (MBBI->getOpcode() == ARM::tBX_RET);
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DebugLoc dl = MBBI->getDebugLoc();
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if (AFI->getReturnRegsCount() <= 3) {
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// Epilogue: pop saved LR to R3 and branch off it.
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// Epilogue for vararg functions: pop LR to R3 and branch off it.
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
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.addReg(ARM::R3, RegState::Define);
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX))
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
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.addReg(ARM::R3, RegState::Kill);
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AddDefaultPred(MIB);
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MIB.copyImplicitOps(&*MBBI);
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// erase the old tBX_RET instruction
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MBB.erase(MBBI);
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} else {
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
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.addReg(ARM::R12, RegState::Define)
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.addReg(ARM::R3, RegState::Kill));
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
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.addReg(ARM::R3, RegState::Define);
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emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
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.addReg(ARM::LR, RegState::Define)
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.addReg(ARM::R3, RegState::Kill));
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
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.addReg(ARM::R3, RegState::Define)
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.addReg(ARM::R12, RegState::Kill));
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// Keep the tBX_RET instruction
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}
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}
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}
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@ -513,9 +476,6 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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// Special epilogue for vararg functions. See emitEpilogue
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if (isVarArg)
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continue;
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// ARMv4T requires BX, see emitEpilogue
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if (STI.hasV4TOps() && !STI.hasV5TOps())
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continue;
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Reg = ARM::PC;
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(*MIB).setDesc(TII.get(ARM::tPOP_RET));
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MIB.copyImplicitOps(&*MI);
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@ -1,205 +0,0 @@
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; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK-V4T
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; RUN: llc -mtriple=thumbv5t-none--eabi < %s | FileCheck %s --check-prefix=CHECK-V5T
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; CHECK-V4T-LABEL: clobberframe
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; CHECK-V5T-LABEL: clobberframe
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define <4 x i32> @clobberframe() #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: push {r4, r5, r7, lr}
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; CHECK-V4T: sub sp,
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; CHECK-V5T: push {r4, r5, r7, lr}
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%b = alloca <4 x i32>, align 16
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%a = alloca <4 x i32>, align 16
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store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
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store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
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%0 = load <4 x i32>* %a, align 16
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ret <4 x i32> %0
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; Epilogue
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; --------
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; CHECK-V4T: add sp,
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; CHECK-V4T-NEXT: pop {r4, r5, r7}
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; CHECK-V4T-NEXT: mov r12, r3
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: mov lr, r3
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; CHECK-V4T-NEXT: mov r3, r12
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; CHECK-V4T: bx lr
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; CHECK-V5T: pop {r4, r5, r7, pc}
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}
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; CHECK-V4T-LABEL: clobbervariadicframe
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; CHECK-V5T-LABEL: clobbervariadicframe
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define <4 x i32> @clobbervariadicframe(i32 %i, ...) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: sub sp,
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; CHECK-V4T: push {r4, r5, r7, lr}
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; CHECK-V5T: sub sp,
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; CHECK-V5T: push {r4, r5, r7, lr}
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%b = alloca <4 x i32>, align 16
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%a = alloca <4 x i32>, align 16
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store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
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store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
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%0 = load <4 x i32>* %a, align 16
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ret <4 x i32> %0
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; Epilogue
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; --------
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; CHECK-V4T: pop {r4, r5, r7}
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; CHECK-V4T-NEXT: mov r12, r3
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: add sp,
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; CHECK-V4T-NEXT: mov lr, r3
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; CHECK-V4T-NEXT: mov r3, r12
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; CHECK-V4T: bx lr
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; CHECK-V5T: add sp,
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; CHECK-V5T-NEXT: pop {r4, r5, r7}
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; CHECK-V5T-NEXT: mov r12, r3
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; CHECK-V5T-NEXT: pop {r3}
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; CHECK-V5T-NEXT: add sp,
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; CHECK-V5T-NEXT: mov lr, r3
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; CHECK-V5T-NEXT: mov r3, r12
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; CHECK-V5T-NEXT: bx lr
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}
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; CHECK-V4T-LABEL: simpleframe
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; CHECK-V5T-LABEL: simpleframe
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define i32 @simpleframe() #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: push {r4, lr}
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; CHECK-V5T: push {r4, lr}
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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%d = alloca i32, align 4
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store i32 1, i32* %a, align 4
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store i32 2, i32* %b, align 4
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store i32 3, i32* %c, align 4
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store i32 4, i32* %d, align 4
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%0 = load i32* %a, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* %a, align 4
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%1 = load i32* %b, align 4
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%inc1 = add nsw i32 %1, 1
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store i32 %inc1, i32* %b, align 4
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%2 = load i32* %c, align 4
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%inc2 = add nsw i32 %2, 1
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store i32 %inc2, i32* %c, align 4
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%3 = load i32* %d, align 4
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%inc3 = add nsw i32 %3, 1
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store i32 %inc3, i32* %d, align 4
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%4 = load i32* %a, align 4
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%5 = load i32* %b, align 4
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%add = add nsw i32 %4, %5
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%6 = load i32* %c, align 4
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%add4 = add nsw i32 %add, %6
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%7 = load i32* %d, align 4
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%add5 = add nsw i32 %add4, %7
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ret i32 %add5
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; Epilogue
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; --------
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; CHECK-V4T: pop {r4}
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; CHECK-V4T: pop {r3}
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; CHECK-V4T: bx r3
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; CHECK-V5T: pop {r4, pc}
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}
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; CHECK-V4T-LABEL: simplevariadicframe
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; CHECK-V5T-LABEL: simplevariadicframe
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define i32 @simplevariadicframe(i32 %i, ...) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T: sub sp,
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; CHECK-V4T: push {r4, r5, r7, lr}
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; CHECK-V4T: sub sp,
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; CHECK-V5T: sub sp,
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; CHECK-V5T: push {r4, r5, r7, lr}
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; CHECK-V5T: sub sp,
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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%d = alloca i32, align 4
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store i32 1, i32* %a, align 4
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store i32 2, i32* %b, align 4
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store i32 3, i32* %c, align 4
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store i32 4, i32* %d, align 4
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%0 = load i32* %a, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* %a, align 4
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%1 = load i32* %b, align 4
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%inc1 = add nsw i32 %1, 1
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store i32 %inc1, i32* %b, align 4
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%2 = load i32* %c, align 4
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%inc2 = add nsw i32 %2, 1
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store i32 %inc2, i32* %c, align 4
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%3 = load i32* %d, align 4
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%inc3 = add nsw i32 %3, 1
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store i32 %inc3, i32* %d, align 4
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%4 = load i32* %a, align 4
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%5 = load i32* %b, align 4
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%add = add nsw i32 %4, %5
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%6 = load i32* %c, align 4
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%add4 = add nsw i32 %add, %6
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%7 = load i32* %d, align 4
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%add5 = add nsw i32 %add4, %7
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%add6 = add nsw i32 %add5, %i
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ret i32 %add6
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; Epilogue
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; --------
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; CHECK-V4T: add sp,
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; CHECK-V4T-NEXT: pop {r4, r5, r7}
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; CHECK-V4T-NEXT: pop {r3}
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; CHECK-V4T-NEXT: add sp,
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; CHECK-V4T-NEXT: bx r3
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; CHECK-V5T: add sp,
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; CHECK-V5T-NEXT: pop {r4, r5, r7}
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; CHECK-V5T-NEXT: pop {r3}
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; CHECK-V5T-NEXT: add sp,
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; CHECK-V5T-NEXT: bx r3
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}
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; CHECK-V4T-LABEL: noframe
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; CHECK-V5T-LABEL: noframe
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define i32 @noframe() #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T-NOT: push
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; CHECK-V5T-NOT: push
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ret i32 0;
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; Epilogue
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; --------
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; CHECK-V4T-NOT: pop
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; CHECK-V5T-NOT: pop
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; CHECK-V4T: bx lr
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; CHECK-V5T: bx lr
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}
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; CHECK-V4T-LABEL: novariadicframe
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; CHECK-V5T-LABEL: novariadicframe
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define i32 @novariadicframe(i32 %i) #0 {
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entry:
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; Prologue
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; --------
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; CHECK-V4T-NOT: push
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; CHECK-V5T-NOT: push
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ret i32 %i;
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; Epilogue
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; --------
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; CHECK-V4T-NOT: pop
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; CHECK-V5T-NOT: pop
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; CHECK-V4T: bx lr
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; CHECK-V5T: bx lr
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}
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