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[RISCV] Add lowering of addressing sequences for PIC
This patch allows lowering of PIC addresses by using PC-relative addressing for DSO-local symbols and accessing the address through the global offset table for non-DSO-local symbols. Differential Revision: https://reviews.llvm.org/D55303 llvm-svn: 363058
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@ -54,9 +54,16 @@ private:
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bool expandAtomicCmpXchg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, bool IsMasked,
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int Width, MachineBasicBlock::iterator &NextMBBI);
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bool expandAuipcInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode);
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bool expandLoadLocalAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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};
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char RISCVExpandPseudo::ID = 0;
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@ -122,6 +129,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
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return expandAtomicCmpXchg(MBB, MBBI, true, 32, NextMBBI);
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case RISCV::PseudoLLA:
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return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
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case RISCV::PseudoLA:
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return expandLoadAddress(MBB, MBBI, NextMBBI);
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}
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return false;
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@ -602,9 +611,10 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
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return true;
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}
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bool RISCVExpandPseudo::expandLoadLocalAddress(
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bool RISCVExpandPseudo::expandAuipcInstPair(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
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unsigned SecondOpcode) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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@ -621,8 +631,8 @@ bool RISCVExpandPseudo::expandLoadLocalAddress(
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MF->insert(++MBB.getIterator(), NewMBB);
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BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
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.addDisp(Symbol, 0, RISCVII::MO_PCREL_HI);
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BuildMI(NewMBB, DL, TII->get(RISCV::ADDI), DestReg)
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.addDisp(Symbol, 0, FlagsHi);
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BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
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.addReg(DestReg)
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.addMBB(NewMBB, RISCVII::MO_PCREL_LO);
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@ -642,6 +652,31 @@ bool RISCVExpandPseudo::expandLoadLocalAddress(
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return true;
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}
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bool RISCVExpandPseudo::expandLoadLocalAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
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RISCV::ADDI);
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}
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bool RISCVExpandPseudo::expandLoadAddress(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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unsigned SecondOpcode;
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unsigned FlagsHi;
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if (MF->getTarget().isPositionIndependent()) {
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const auto &STI = MF->getSubtarget<RISCVSubtarget>();
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SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
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FlagsHi = RISCVII::MO_GOT_HI;
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} else {
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SecondOpcode = RISCV::ADDI;
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FlagsHi = RISCVII::MO_PCREL_HI;
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}
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return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi, SecondOpcode);
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}
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} // end of anonymous namespace
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INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
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@ -403,10 +403,25 @@ static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
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}
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template <class NodeTy>
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SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG) const {
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SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
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bool IsLocal) const {
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SDLoc DL(N);
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EVT Ty = getPointerTy(DAG.getDataLayout());
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if (isPositionIndependent()) {
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SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
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if (IsLocal)
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// Use PC-relative addressing to access the symbol. This generates the
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// pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
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// %pcrel_lo(auipc)).
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return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
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// Use PC-relative addressing to access the GOT for this symbol, then load
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// the address from the GOT. This generates the pattern (PseudoLA sym),
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// which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
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return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
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}
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switch (getTargetMachine().getCodeModel()) {
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default:
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report_fatal_error("Unsupported code model for lowering");
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@ -436,10 +451,9 @@ SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
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int64_t Offset = N->getOffset();
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MVT XLenVT = Subtarget.getXLenVT();
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if (isPositionIndependent())
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report_fatal_error("Unable to lowerGlobalAddress");
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SDValue Addr = getAddr(N, DAG);
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const GlobalValue *GV = N->getGlobal();
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bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
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SDValue Addr = getAddr(N, DAG, IsLocal);
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// In order to maximise the opportunity for common subexpression elimination,
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// emit a separate ADD node for the global address offset instead of folding
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@ -455,9 +469,6 @@ SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
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SelectionDAG &DAG) const {
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BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
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if (isPositionIndependent())
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report_fatal_error("Unable to lowerBlockAddress");
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return getAddr(N, DAG);
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}
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@ -465,9 +476,6 @@ SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
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SelectionDAG &DAG) const {
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ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
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if (isPositionIndependent())
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report_fatal_error("Unable to lowerConstantPool");
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return getAddr(N, DAG);
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}
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@ -155,7 +155,7 @@ private:
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}
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template <class NodeTy>
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SDValue getAddr(NodeTy *N, SelectionDAG &DAG) const;
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SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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@ -439,6 +439,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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case RISCV::PseudoCALL:
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case RISCV::PseudoTAIL:
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case RISCV::PseudoLLA:
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case RISCV::PseudoLA:
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return 8;
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case TargetOpcode::INLINEASM:
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case TargetOpcode::INLINEASM_BR: {
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@ -51,6 +51,9 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
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case RISCVII::MO_PCREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
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break;
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case RISCVII::MO_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
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break;
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}
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const MCExpr *ME =
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@ -53,6 +53,7 @@ enum {
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MO_HI,
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MO_PCREL_LO,
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MO_PCREL_HI,
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MO_GOT_HI,
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};
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} // namespace RISCVII
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85
test/CodeGen/RISCV/pic-models.ll
Normal file
85
test/CodeGen/RISCV/pic-models.ll
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@ -0,0 +1,85 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -relocation-model=static < %s \
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; RUN: | FileCheck -check-prefix=RV32-STATIC %s
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; RUN: llc -mtriple=riscv32 -relocation-model=pic < %s \
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; RUN: | FileCheck -check-prefix=RV32-PIC %s
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; RUN: llc -mtriple=riscv64 -relocation-model=static < %s \
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; RUN: | FileCheck -check-prefix=RV64-STATIC %s
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; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s \
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; RUN: | FileCheck -check-prefix=RV64-PIC %s
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; Check basic lowering of PIC addressing.
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; TODO: Check other relocation models?
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@external_var = external global i32
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@internal_var = internal global i32 42
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; external address
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define i32* @f1() nounwind {
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; RV32-STATIC-LABEL: f1:
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; RV32-STATIC: # %bb.0: # %entry
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; RV32-STATIC-NEXT: lui a0, %hi(external_var)
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; RV32-STATIC-NEXT: addi a0, a0, %lo(external_var)
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; RV32-STATIC-NEXT: ret
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;
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; RV32-PIC-LABEL: f1:
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; RV32-PIC: # %bb.0: # %entry
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; RV32-PIC-NEXT: .LBB0_1: # %entry
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; RV32-PIC-NEXT: # Label of block must be emitted
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; RV32-PIC-NEXT: auipc a0, %got_pcrel_hi(external_var)
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; RV32-PIC-NEXT: lw a0, %pcrel_lo(.LBB0_1)(a0)
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; RV32-PIC-NEXT: ret
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;
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; RV64-STATIC-LABEL: f1:
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; RV64-STATIC: # %bb.0: # %entry
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; RV64-STATIC-NEXT: lui a0, %hi(external_var)
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; RV64-STATIC-NEXT: addi a0, a0, %lo(external_var)
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; RV64-STATIC-NEXT: ret
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;
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; RV64-PIC-LABEL: f1:
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; RV64-PIC: # %bb.0: # %entry
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; RV64-PIC-NEXT: .LBB0_1: # %entry
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; RV64-PIC-NEXT: # Label of block must be emitted
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; RV64-PIC-NEXT: auipc a0, %got_pcrel_hi(external_var)
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; RV64-PIC-NEXT: ld a0, %pcrel_lo(.LBB0_1)(a0)
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; RV64-PIC-NEXT: ret
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entry:
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ret i32* @external_var
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}
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; internal address
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define i32* @f2() nounwind {
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; RV32-STATIC-LABEL: f2:
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; RV32-STATIC: # %bb.0: # %entry
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; RV32-STATIC-NEXT: lui a0, %hi(internal_var)
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; RV32-STATIC-NEXT: addi a0, a0, %lo(internal_var)
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; RV32-STATIC-NEXT: ret
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;
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; RV32-PIC-LABEL: f2:
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; RV32-PIC: # %bb.0: # %entry
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; RV32-PIC-NEXT: .LBB1_1: # %entry
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; RV32-PIC-NEXT: # Label of block must be emitted
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; RV32-PIC-NEXT: auipc a0, %pcrel_hi(internal_var)
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; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
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; RV32-PIC-NEXT: ret
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;
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; RV64-STATIC-LABEL: f2:
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; RV64-STATIC: # %bb.0: # %entry
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; RV64-STATIC-NEXT: lui a0, %hi(internal_var)
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; RV64-STATIC-NEXT: addi a0, a0, %lo(internal_var)
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; RV64-STATIC-NEXT: ret
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;
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; RV64-PIC-LABEL: f2:
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; RV64-PIC: # %bb.0: # %entry
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; RV64-PIC-NEXT: .LBB1_1: # %entry
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; RV64-PIC-NEXT: # Label of block must be emitted
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; RV64-PIC-NEXT: auipc a0, %pcrel_hi(internal_var)
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; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
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; RV64-PIC-NEXT: ret
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entry:
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ret i32* @internal_var
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}
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