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https://github.com/RPCS3/llvm-mirror.git
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Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC
llvm-svn: 333961
This commit is contained in:
Amaury Sechet
parent
54c1ba8142
commit
57672b8208
@ -4,38 +4,39 @@
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; rdar://11314175: SD Scheduler, BuildSchedUnits assert:
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; N->getNodeId() == -1 && "Node already inserted!
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define void @func() nounwind ssp {
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define void @func(<4 x float> %a, <16 x i8> %b, <16 x i8> %c, <8 x float> %d, <8 x float> %e, <8 x float>* %f) nounwind ssp {
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; CHECK-LABEL: func:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vmovups 0, %xmm0
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; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; CHECK-NEXT: vblendps {{.*#+}} ymm2 = ymm0[0,1,2,3],ymm1[4,5,6,7]
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; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
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; CHECK-NEXT: vbroadcastss 32, %xmm3
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; CHECK-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
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; CHECK-NEXT: vmulps %ymm2, %ymm2, %ymm2
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; CHECK-NEXT: vmovdqu 0, %xmm3
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; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0
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; CHECK-NEXT: vpalignr {{.*#+}} xmm1 = xmm3[4,5,6,7,8,9,10,11,12,13,14,15],xmm1[0,1,2,3]
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; CHECK-NEXT: vmovdqu 32, %xmm3
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; CHECK-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[4,5,6,7,8,9,10,11,12,13,14,15],xmm3[0,1,2,3]
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; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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; CHECK-NEXT: vmulps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
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; CHECK-NEXT: vmulps %ymm1, %ymm1, %ymm1
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; CHECK-NEXT: vaddps %ymm1, %ymm0, %ymm0
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; CHECK-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: vmulps %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = zero,zero,ymm0[0,1]
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; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; CHECK-NEXT: vaddps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: vhaddps %ymm4, %ymm0, %ymm0
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; CHECK-NEXT: vsubps %ymm0, %ymm0, %ymm0
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; CHECK-NEXT: vhaddps %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: vmovaps %ymm0, (%rax)
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; CHECK-NEXT: vmovaps %ymm0, (%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%tmp = load <4 x float>, <4 x float>* null, align 1
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%tmp14 = getelementptr <4 x float>, <4 x float>* null, i32 2
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%tmp15 = load <4 x float>, <4 x float>* %tmp14, align 1
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%tmp16 = shufflevector <4 x float> %tmp, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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%tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1)
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%tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> %a, i8 1)
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%tmp18 = bitcast <4 x float> %tmp to <16 x i8>
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%tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> %b, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp20 = bitcast <16 x i8> %tmp19 to <4 x float>
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%tmp21 = bitcast <4 x float> %tmp15 to <16 x i8>
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%tmp22 = shufflevector <16 x i8> undef, <16 x i8> %tmp21, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp22 = shufflevector <16 x i8> %c, <16 x i8> %tmp21, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp23 = bitcast <16 x i8> %tmp22 to <4 x float>
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%tmp24 = shufflevector <4 x float> %tmp20, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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%tmp25 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp24, <4 x float> %tmp23, i8 1)
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@ -43,14 +44,14 @@ define void @func() nounwind ssp {
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%tmp27 = fmul <8 x float> %tmp25, %tmp25
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%tmp28 = fadd <8 x float> %tmp26, %tmp27
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%tmp29 = fadd <8 x float> %tmp28, %tmp28
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%tmp30 = shufflevector <8 x float> %tmp29, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp30 = shufflevector <8 x float> %tmp29, <8 x float> %d, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp31 = fmul <4 x float> %tmp30, %tmp30
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%tmp32 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> zeroinitializer, <4 x float> %tmp31, i8 1)
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%tmp33 = fadd <8 x float> %tmp32, %tmp32
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%tmp34 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %tmp33, <8 x float> undef) nounwind
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%tmp34 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %tmp33, <8 x float> %e) nounwind
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%tmp35 = fsub <8 x float> %tmp34, %tmp34
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%tmp36 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> zeroinitializer, <8 x float> %tmp35) nounwind
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store <8 x float> %tmp36, <8 x float>* undef, align 32
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store <8 x float> %tmp36, <8 x float>* %f, align 32
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ret void
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}
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@ -5,48 +5,55 @@
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @test() local_unnamed_addr {
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define void @test(<4x i64> %a, <4 x x86_fp80> %b, <8 x x86_fp80>* %c) local_unnamed_addr {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,3]
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; CHECK-NEXT: vpextrq $1, %xmm0, %rax
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; CHECK-NEXT: vpextrq $1, %xmm0, %r8
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [2,3]
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; CHECK-NEXT: vmovq %xmm1, %r9
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm2
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; CHECK-NEXT: vmovq %xmm2, %rdx
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; CHECK-NEXT: vpextrq $1, %xmm1, %rsi
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; CHECK-NEXT: vpextrq $1, %xmm2, %rax
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; CHECK-NEXT: vmovq %xmm0, %rcx
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; CHECK-NEXT: negq %rdx
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; CHECK-NEXT: negq %rcx
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; CHECK-NEXT: fld1
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; CHECK-NEXT: fldz
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; CHECK-NEXT: fld %st(0)
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; CHECK-NEXT: fcmove %st(2), %st(0)
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; CHECK-NEXT: cmpq %rax, %rcx
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; CHECK-NEXT: cmpq %rax, %rsi
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; CHECK-NEXT: fld %st(1)
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; CHECK-NEXT: fcmove %st(3), %st(0)
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; CHECK-NEXT: cmpq %rax, %rax
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; CHECK-NEXT: cmpq %rdx, %r9
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; CHECK-NEXT: fld %st(2)
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; CHECK-NEXT: fcmove %st(4), %st(0)
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmpq %rax, %rax
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; CHECK-NEXT: cmpq %r8, %rax
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; CHECK-NEXT: fxch %st(3)
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; CHECK-NEXT: fcmove %st(4), %st(0)
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; CHECK-NEXT: fstp %st(4)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt 70(%rdi)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt 50(%rdi)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt 30(%rdi)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt 10(%rdi)
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; CHECK-NEXT: fadd %st(0), %st(0)
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; CHECK-NEXT: fstpt 60(%rdi)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fadd %st(0), %st(0)
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; CHECK-NEXT: fxch %st(3)
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; CHECK-NEXT: fadd %st(0), %st(0)
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; CHECK-NEXT: fxch %st(2)
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; CHECK-NEXT: fadd %st(0), %st(0)
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; CHECK-NEXT: fstpt 40(%rdi)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fadd %st(0), %st(0)
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; CHECK-NEXT: fxch %st(3)
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; CHECK-NEXT: fstpt (%rax)
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; CHECK-NEXT: fxch %st(2)
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; CHECK-NEXT: fstpt (%rax)
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; CHECK-NEXT: fxch %st(1)
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; CHECK-NEXT: fstpt (%rax)
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; CHECK-NEXT: fstpt (%rax)
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%1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, undef
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; CHECK-NEXT: fstpt 20(%rdi)
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; CHECK-NEXT: fadd %st(0), %st(0)
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; CHECK-NEXT: fstpt (%rdi)
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%1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, %a
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%2 = select <4 x i1> %1, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer
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%3 = fadd <4 x x86_fp80> %2, %2
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%4 = shufflevector <4 x x86_fp80> %3, <4 x x86_fp80> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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store <8 x x86_fp80> %4, <8 x x86_fp80>* undef, align 16
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%4 = shufflevector <4 x x86_fp80> %3, <4 x x86_fp80> %b, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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store <8 x x86_fp80> %4, <8 x x86_fp80>* %c, align 16
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unreachable
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}
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