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R600/SI: Define a schedule model
The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. llvm-svn: 225913
This commit is contained in:
Tom Stellard
parent
c3dc6a8739
commit
577d33b096
@ -83,34 +83,38 @@ def : Proc<"cayman", R600_VLIW4_Itin,
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// Southern Islands
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//===----------------------------------------------------------------------===//
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def : Proc<"SI", SI_Itin, [FeatureSouthernIslands]>;
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def : ProcessorModel<"SI", SIFullSpeedModel, [FeatureSouthernIslands]>;
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def : Proc<"tahiti", SI_Itin, [FeatureSouthernIslands]>;
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def : ProcessorModel<"tahiti", SIFullSpeedModel, [FeatureSouthernIslands]>;
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def : Proc<"pitcairn", SI_Itin, [FeatureSouthernIslands]>;
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def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
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def : Proc<"verde", SI_Itin, [FeatureSouthernIslands]>;
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def : ProcessorModel<"verde", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
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def : Proc<"oland", SI_Itin, [FeatureSouthernIslands]>;
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def : ProcessorModel<"oland", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
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def : Proc<"hainan", SI_Itin, [FeatureSouthernIslands]>;
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def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
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//===----------------------------------------------------------------------===//
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// Sea Islands
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//===----------------------------------------------------------------------===//
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def : Proc<"bonaire", SI_Itin, [FeatureSeaIslands]>;
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def : ProcessorModel<"bonaire", SIQuarterSpeedModel, [FeatureSeaIslands]>;
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def : Proc<"kabini", SI_Itin, [FeatureSeaIslands]>;
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def : ProcessorModel<"kabini", SIQuarterSpeedModel, [FeatureSeaIslands]>;
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def : Proc<"kaveri", SI_Itin, [FeatureSeaIslands]>;
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def : ProcessorModel<"kaveri", SIQuarterSpeedModel, [FeatureSeaIslands]>;
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def : Proc<"hawaii", SI_Itin, [FeatureSeaIslands]>;
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def : ProcessorModel<"hawaii", SIFullSpeedModel, [FeatureSeaIslands]>;
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def : Proc<"mullins", SI_Itin, [FeatureSeaIslands]>;
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def : ProcessorModel<"mullins", SIQuarterSpeedModel, [FeatureSeaIslands]>;
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def : Proc<"tonga", SI_Itin, [FeatureVolcanicIslands]>;
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//===----------------------------------------------------------------------===//
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// Volcanic Islands
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//===----------------------------------------------------------------------===//
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def : Proc<"iceland", SI_Itin, [FeatureVolcanicIslands]>;
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def : ProcessorModel<"tonga", SIFullSpeedModel, [FeatureVolcanicIslands]>;
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def : Proc<"carrizo", SI_Itin, [FeatureVolcanicIslands]>;
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def : ProcessorModel<"iceland", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
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def : ProcessorModel<"carrizo", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
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@ -68,6 +68,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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// Most instructions require adjustments after selection to satisfy
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// operand requirements.
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let hasPostISelHook = 1;
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let SchedRW = [Write32Bit];
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}
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class Enc32 {
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@ -214,9 +215,9 @@ class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
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let Inst{31-27} = 0x18; //encoding
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}
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let SchedRW = [WriteSALU] in {
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class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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@ -274,6 +275,8 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
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let UseNamedOperandTable = 1;
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}
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} // let SchedRW = [WriteSALU]
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class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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@ -283,6 +286,7 @@ class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
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let mayLoad = 1;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteSMEM];
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}
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//===----------------------------------------------------------------------===//
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@ -588,6 +592,7 @@ class DS <dag outs, dag ins, string asm, list<dag> pattern> :
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let DS = 1;
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let UseNamedOperandTable = 1;
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let DisableEncoding = "$m0";
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let SchedRW = [WriteLDS];
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}
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class DS_si <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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@ -602,6 +607,7 @@ class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteVMEM];
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}
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class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
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@ -613,6 +619,7 @@ class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteVMEM];
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}
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class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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@ -641,5 +648,4 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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}
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} // End Uses = [EXEC]
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@ -1191,6 +1191,8 @@ defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
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let Uses = [EXEC] in {
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// FIXME: Specify SchedRW for READFIRSTLANE_B32
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def V_READFIRSTLANE_B32 : VOP1 <
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0x00000002,
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(outs SReg_32:$vdst),
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@ -1201,6 +1203,8 @@ def V_READFIRSTLANE_B32 : VOP1 <
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}
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let SchedRW = [WriteQuarterRate32] in {
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defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
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VOP_I32_F64, fp_to_sint
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>;
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@ -1253,6 +1257,9 @@ defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
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defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
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VOP_F64_I32, uint_to_fp
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>;
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} // let SchedRW = [WriteQuarterRate32]
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defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32",
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VOP_F32_F32, AMDGPUfract
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>;
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@ -1271,6 +1278,9 @@ defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32",
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defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32",
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VOP_F32_F32, fexp2
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>;
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let SchedRW = [WriteQuarterRate32] in {
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defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32",
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VOP_F32_F32, flog2
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>;
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@ -1283,18 +1293,32 @@ defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32",
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defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32",
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VOP_F32_F32, AMDGPUrsq
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>;
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} //let SchedRW = [WriteQuarterRate32]
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let SchedRW = [WriteDouble] in {
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defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64",
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VOP_F64_F64, AMDGPUrcp
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>;
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defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64",
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VOP_F64_F64, AMDGPUrsq
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>;
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} // let SchedRW = [WriteDouble];
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defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32",
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VOP_F32_F32, fsqrt
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>;
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let SchedRW = [WriteDouble] in {
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defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64",
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VOP_F64_F64, fsqrt
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>;
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} // let SchedRW = [WriteDouble]
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defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32",
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VOP_F32_F32, AMDGPUsin
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>;
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@ -1323,6 +1347,8 @@ defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>
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// These instruction only exist on SI and CI
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let SubtargetPredicate = isSICI in {
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let SchedRW = [WriteQuarterRate32] in {
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defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", VOP_F32_F32>;
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defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
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defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>;
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@ -1332,17 +1358,25 @@ defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32",
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defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32",
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VOP_F32_F32, AMDGPUrsq_legacy
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>;
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} // End let SchedRW = [WriteQuarterRate32]
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let SchedRW = [WriteDouble] in {
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defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
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defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64",
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VOP_F64_F64, AMDGPUrsq_clamped
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>;
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} // End SchedRW = [WriteDouble]
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} // End SubtargetPredicate = isSICI
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//===----------------------------------------------------------------------===//
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// VINTRP Instructions
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//===----------------------------------------------------------------------===//
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// FIXME: Specify SchedRW for VINTRP insturctions.
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defm V_INTERP_P1_F32 : VINTRP_m <
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0x00000000, "v_interp_p1_f32",
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(outs VGPR_32:$dst),
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@ -1656,11 +1690,15 @@ defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32",
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defm V_DIV_FIXUP_F32 : VOP3Inst <
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vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
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>;
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let SchedRW = [WriteDouble] in {
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defm V_DIV_FIXUP_F64 : VOP3Inst <
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vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
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>;
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// Only on SI
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} // let SchedRW = [WriteDouble]
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defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64",
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VOP_I64_I64_I32, shl
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>;
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@ -1675,6 +1713,7 @@ defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64",
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VOP_I64_I64_I32, sra
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>;
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let SchedRW = [WriteDouble] in {
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let isCommutable = 1 in {
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defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64",
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@ -1697,7 +1736,9 @@ defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64",
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VOP_F64_F64_I32, AMDGPUldexp
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>;
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let isCommutable = 1 in {
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} // let SchedRW = [WriteDouble]
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let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
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defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
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VOP_I32_I32_I32
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@ -1713,30 +1754,37 @@ defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
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VOP_I32_I32_I32
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>;
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} // isCommutable = 1
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} // isCommutable = 1, SchedRW = [WriteQuarterRate32]
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defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>;
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let SchedRW = [WriteDouble] in {
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// Double precision division pre-scale.
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defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>;
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} // let SchedRW = [WriteDouble]
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let isCommutable = 1 in {
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defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32",
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VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
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>;
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let SchedRW = [WriteDouble] in {
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defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64",
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VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
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>;
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} // End SchedRW = [WriteDouble]
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} // End isCommutable = 1
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//def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>;
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//def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>;
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//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
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let SchedRW = [WriteDouble] in {
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defm V_TRIG_PREOP_F64 : VOP3Inst <
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vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
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>;
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} // let SchedRW = [WriteDouble]
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//===----------------------------------------------------------------------===//
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// Pseudo Instructions
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//===----------------------------------------------------------------------===//
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@ -7,9 +7,85 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// TODO: This is just a place holder for now.
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// MachineModel definitions for Southern Islands (SI)
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//
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//===----------------------------------------------------------------------===//
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def WriteBranch : SchedWrite;
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def WriteExport : SchedWrite;
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def WriteLDS : SchedWrite;
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def WriteSALU : SchedWrite;
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def WriteSMEM : SchedWrite;
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def WriteVMEM : SchedWrite;
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def SI_Itin : ProcessorItineraries <[], [], []>;
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// Vector ALU instructions
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def Write32Bit : SchedWrite;
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def WriteQuarterRate32 : SchedWrite;
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def WriteFloatFMA : SchedWrite;
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def WriteDouble : SchedWrite;
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def WriteDoubleAdd : SchedWrite;
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def SIFullSpeedModel : SchedMachineModel;
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def SIQuarterSpeedModel : SchedMachineModel;
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// BufferSize = 0 means the processors are in-order.
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let BufferSize = 0 in {
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// XXX: Are the resource counts correct?
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def HWBranch : ProcResource<1>;
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def HWExport : ProcResource<7>; // Taken from S_WAITCNT
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def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT
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def HWSALU : ProcResource<1>;
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def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT
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def HWVALU : ProcResource<1>;
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}
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class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
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int latency> : WriteRes<write, resources> {
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let Latency = latency;
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}
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class HWVALUWriteRes<SchedWrite write, int latency> :
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HWWriteRes<write, [HWVALU], latency>;
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// The latency numbers are taken from AMD Accelerated Parallel Processing
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// guide. They may not be acurate.
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// The latency values are 1 / (operations / cycle) / 4.
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multiclass SICommonWriteRes {
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def : HWWriteRes<WriteBranch, [HWBranch], 100>; // XXX: Guessed ???
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def : HWWriteRes<WriteExport, [HWExport], 100>; // XXX: Guessed ???
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def : HWWriteRes<WriteLDS, [HWLGKM], 32>; // 2 - 64
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def : HWWriteRes<WriteSALU, [HWSALU], 1>;
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def : HWWriteRes<WriteSMEM, [HWLGKM], 10>; // XXX: Guessed ???
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def : HWWriteRes<WriteVMEM, [HWVMEM], 450>; // 300 - 600
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def : HWVALUWriteRes<Write32Bit, 1>;
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def : HWVALUWriteRes<WriteQuarterRate32, 4>;
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}
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let SchedModel = SIFullSpeedModel in {
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defm : SICommonWriteRes;
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def : HWVALUWriteRes<WriteFloatFMA, 1>;
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def : HWVALUWriteRes<WriteDouble, 4>;
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def : HWVALUWriteRes<WriteDoubleAdd, 2>;
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} // End SchedModel = SIFullSpeedModel
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let SchedModel = SIQuarterSpeedModel in {
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defm : SICommonWriteRes;
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def : HWVALUWriteRes<WriteFloatFMA, 16>;
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def : HWVALUWriteRes<WriteDouble, 16>;
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def : HWVALUWriteRes<WriteDoubleAdd, 8>;
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} // End SchedModel = SIQuarterSpeedModel
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