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[ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCI
This is a cleanup commit similar to r271555, but for ARM. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. Since the ARM backend seems to have quite a lot of calls to these methods, I intend to submit 5-6 subtarget features at a time, instead of one big lump. Differential Revision: http://reviews.llvm.org/D21432 llvm-svn: 273544
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Diana Picus
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396e4cbe72
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@ -106,6 +106,44 @@ def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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// Whether or not it may be profitable to unpredicate certain instructions
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// during if conversion.
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def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
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"IsProfitableToUnpredicate",
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"true",
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"Is profitable to unpredicate">;
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// Some targets (e.g. Swift) have microcoded VGETLNi32.
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def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
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"HasSlowVGETLNi32", "true",
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"Has slow VGETLNi32 - prefer VMOV">;
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// Some targets (e.g. Swift) have microcoded VDUP32.
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def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
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"Has slow VDUP32 - prefer VMOV">;
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// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
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// for scalar FP, as this allows more effective execution domain optimization.
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def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
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"true", "Prefer VMOVSR">;
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// Swift has ISHST barriers compatible with Atomic Release semantics but weaker
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// than ISH
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def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
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"true", "Prefer ISHST barriers">;
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// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
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// VFP to NEON, as an execution domain optimization.
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def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
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"true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations. This affects instruction selection and should
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// only be enabled if the handling of denormals is not important.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Some processors have FP multiply-accumulate instructions that don't
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// play nicely with other VFP / NEON instructions, and it's generally better
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// to just not use them.
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@ -117,12 +155,6 @@ def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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@ -533,6 +565,8 @@ def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
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FeatureT2XtPk,
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FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeaturePreferVMOVSR,
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FeatureNEONForFPMovs,
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FeatureMP]>;
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// FIXME: A12 has currently the same Schedule model as A9
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@ -596,7 +630,11 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
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FeatureHWDivARM,
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FeatureAvoidPartialCPSR,
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FeatureAvoidMOVsShOp,
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FeatureHasSlowFPVMLx]>;
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FeatureHasSlowFPVMLx,
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FeatureProfUnpredicate,
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FeaturePrefISHSTBarrier,
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FeatureSlowVGETLNi32,
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FeatureSlowVDUP32]>;
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// FIXME: R4 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
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@ -1766,9 +1766,9 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
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bool
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ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const {
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// Reduce false anti-dependencies to let Swift's out-of-order execution
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// Reduce false anti-dependencies to let the target's out-of-order execution
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// engine do its thing.
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return Subtarget.isSwift();
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return Subtarget.isProfitableToUnpredicate();
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}
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/// getInstrPredicate - If instruction is predicated, returns its predicate
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@ -4178,7 +4178,7 @@ ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
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// CortexA9 is particularly picky about mixing the two and wants these
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// converted.
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if (Subtarget.isCortexA9() && !isPredicated(*MI) &&
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if (Subtarget.useNEONForFPMovs() && !isPredicated(*MI) &&
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(MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
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MI->getOpcode() == ARM::VMOVS))
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return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
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@ -3024,7 +3024,8 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
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if (Subtarget->isMClass()) {
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// Only a full system barrier exists in the M-class architectures.
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Domain = ARM_MB::SY;
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} else if (Subtarget->isSwift() && Ord == AtomicOrdering::Release) {
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} else if (Subtarget->preferISHSTBarriers() &&
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Ord == AtomicOrdering::Release) {
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// Swift happens to implement ISHST barriers in a way that's compatible with
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// Release semantics but weaker than ISH so we'd be fools not to use
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// it. Beware: other processors probably don't!
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@ -12236,7 +12237,7 @@ Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
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/*FALLTHROUGH*/
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case AtomicOrdering::Release:
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case AtomicOrdering::AcquireRelease:
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if (Subtarget->isSwift())
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if (Subtarget->preferISHSTBarriers())
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return makeDMB(Builder, ARM_MB::ISHST);
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// FIXME: add a comment with a link to documentation justifying this.
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else
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@ -321,19 +321,16 @@ def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
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" Subtarget->hasVFP4()) || "
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"Subtarget->isTargetDarwin()">;
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// VGETLNi32 is microcoded on Swift - prefer VMOV.
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def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
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def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
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def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">;
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def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">;
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// VDUP.32 is microcoded on Swift - prefer VMOV.
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def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
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def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
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def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">;
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def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">;
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// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
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// this allows more effective execution domain optimization. See
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// setExecutionDomain().
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def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
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def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
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def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||"
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"!Subtarget->useNEONForSinglePrecisionFP()">;
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def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&"
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"Subtarget->useNEONForSinglePrecisionFP()">;
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def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
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def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">;
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@ -154,6 +154,12 @@ void ARMSubtarget::initializeEnvironment() {
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HasCRC = false;
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HasRAS = false;
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HasZeroCycleZeroing = false;
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IsProfitableToUnpredicate = false;
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HasSlowVGETLNi32 = false;
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HasSlowVDUP32 = false;
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PreferVMOVSR = false;
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PreferISHST = false;
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UseNEONForFPMovs = false;
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StrictAlign = false;
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HasDSP = false;
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UseNaClTrap = false;
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@ -218,6 +218,24 @@ protected:
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/// particularly effective at zeroing a VFP register.
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bool HasZeroCycleZeroing;
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/// If true, if conversion may decide to leave some instructions unpredicated.
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bool IsProfitableToUnpredicate;
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/// If true, VMOV will be favored over VGETLNi32.
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bool HasSlowVGETLNi32;
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/// If true, VMOV will be favored over VDUP.
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bool HasSlowVDUP32;
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/// If true, VMOVSR will be favored over VMOVDRR.
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bool PreferVMOVSR;
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/// If true, ISHST barriers will be used for Release semantics.
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bool PreferISHST;
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/// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
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bool UseNEONForFPMovs;
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/// StrictAlign - If true, the subtarget disallows unaligned memory
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/// accesses for some types. For details, see
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/// ARMTargetLowering::allowsMisalignedMemoryAccesses().
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@ -376,6 +394,12 @@ public:
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bool hasTrustZone() const { return HasTrustZone; }
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bool has8MSecExt() const { return Has8MSecExt; }
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bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
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bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
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bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
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bool hasSlowVDUP32() const { return HasSlowVDUP32; }
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bool preferVMOVSR() const { return PreferVMOVSR; }
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bool preferISHSTBarriers() const { return PreferISHST; }
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bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
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bool prefers32BitThumb() const { return Pref32BitThumb; }
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bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
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bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
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