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AMDGPU/GlobalISel: Select S16->S32 fptoint
llvm-svn: 371950
This commit is contained in:
Matt Arsenault
parent
62c32a2fa8
commit
57b65f272d
@ -422,7 +422,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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.scalarize(0);
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalFor({{S32, S32}, {S32, S64}})
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.legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
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.scalarize(0);
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getActionDefinitionsBuilder(G_INTRINSIC_ROUND)
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@ -743,12 +743,12 @@ def : GCNPat <
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def : GCNPat <
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(i32 (fp_to_sint f16:$src)),
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(V_CVT_I32_F32_e32 (V_CVT_F32_F16_e32 $src))
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(V_CVT_I32_F32_e32 (V_CVT_F32_F16_e32 VSrc_b32:$src))
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>;
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def : GCNPat <
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(i32 (fp_to_uint f16:$src)),
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(V_CVT_U32_F32_e32 (V_CVT_F32_F16_e32 $src))
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(V_CVT_U32_F32_e32 (V_CVT_F32_F16_e32 VSrc_b32:$src))
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>;
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def : GCNPat <
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132
test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
Normal file
132
test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
Normal file
@ -0,0 +1,132 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
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---
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name: fptosi_s32_to_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fptosi_s32_to_s32_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FPTOSI %0
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$vgpr0 = COPY %1
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...
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---
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name: fptosi_s32_to_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fptosi_s32_to_s32_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_FPTOSI %0
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$vgpr0 = COPY %1
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...
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---
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name: fptosi_s32_to_s32_fneg_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FNEG %0
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%2:vgpr(s32) = G_FPTOSI %1
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$vgpr0 = COPY %2
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...
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---
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name: fptosi_s16_to_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fptosi_s16_to_s32_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
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; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_FPTOSI %1
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$vgpr0 = COPY %2
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...
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---
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name: fptosi_s16_to_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fptosi_s16_to_s32_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
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; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_FPTOSI %1
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$vgpr0 = COPY %2
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...
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---
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name: fptosi_s16_to_s32_fneg_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
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; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FNEG %1
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%3:vgpr(s32) = G_FPTOSI %2
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$vgpr0 = COPY %3
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...
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@ -1,3 +1,4 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
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---
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@ -6,27 +7,99 @@ name: fptoui
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: fptoui
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
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; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN-LABEL: name: fptoui
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
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; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $exec
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; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
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; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
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%0:sgpr(s32) = COPY $sgpr0
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; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(p1) = COPY $vgpr3_vgpr4
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; fptoui s
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; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
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%3:vgpr(s32) = G_FPTOUI %0
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; fptoui v
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; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
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%4:vgpr(s32) = G_FPTOUI %1
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G_STORE %3, %2 :: (store 4, addrspace 1)
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G_STORE %4, %2 :: (store 4, addrspace 1)
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...
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---
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name: fptoui_s16_to_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fptoui_s16_to_s32_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
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; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_FPTOUI %1
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$vgpr0 = COPY %2
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...
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---
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name: fptoui_s16_to_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fptoui_s16_to_s32_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
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; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_FPTOUI %1
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$vgpr0 = COPY %2
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...
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---
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name: fptoui_s16_to_s32_fneg_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
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; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FNEG %1
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%3:vgpr(s32) = G_FPTOUI %2
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$vgpr0 = COPY %3
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...
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