diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp
index e912ebcfc12..859d3288db8 100644
--- a/lib/Target/X86/X86InstructionSelector.cpp
+++ b/lib/Target/X86/X86InstructionSelector.cpp
@@ -642,7 +642,7 @@ bool X86InstructionSelector::selectZext(MachineInstr &I,
 
   unsigned AndOpc;
   if (DstTy == LLT::scalar(8))
-    AndOpc = X86::AND8ri8;
+    AndOpc = X86::AND8ri;
   else if (DstTy == LLT::scalar(16))
     AndOpc = X86::AND16ri8;
   else if (DstTy == LLT::scalar(32))
diff --git a/test/CodeGen/X86/GlobalISel/select-ext.mir b/test/CodeGen/X86/GlobalISel/select-ext.mir
index d8d48f627a7..b6734e5aa2b 100644
--- a/test/CodeGen/X86/GlobalISel/select-ext.mir
+++ b/test/CodeGen/X86/GlobalISel/select-ext.mir
@@ -51,7 +51,7 @@ registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
 # ALL:          %0 = COPY %dil
-# ALL-NEXT:     %1 = AND8ri8 %0, 1, implicit-def %eflags
+# ALL-NEXT:     %1 = AND8ri %0, 1, implicit-def %eflags
 # ALL-NEXT:     %al = COPY %1
 # ALL-NEXT:     RET 0, implicit %al
 body:             |