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When lowering certain atomics, we need to copy the memoperand from the old

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atomic operation to the new one.

llvm-svn: 53714
This commit is contained in:
Mon P Wang 2008-07-17 04:54:06 +00:00
parent 41aeb22c1d
commit 57cd9d6e5a
1 changed files with 5 additions and 1 deletions
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6
lib/Target/X86/X86ISelLowering.cpp
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@ -6010,7 +6010,9 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
for (int i=0; i <= lastAddrIndx; ++i) for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]); (*MIB).addOperand(*argOpers[i]);
MIB.addReg(t2); MIB.addReg(t2);
assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
(*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
MIB.addReg(X86::EAX); MIB.addReg(X86::EAX);
@ -6107,6 +6109,8 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
for (int i=0; i <= lastAddrIndx; ++i) for (int i=0; i <= lastAddrIndx; ++i)
(*MIB).addOperand(*argOpers[i]); (*MIB).addOperand(*argOpers[i]);
MIB.addReg(t3); MIB.addReg(t3);
assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
(*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg()); MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
MIB.addReg(X86::EAX); MIB.addReg(X86::EAX);