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AMDGPU: Fix assert on n inline asm constraint
llvm-svn: 310515
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25cf33c6db
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@ -1017,20 +1017,29 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
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bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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unsigned AsmVariant,
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const char *ExtraCode, raw_ostream &O) {
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const char *ExtraCode, raw_ostream &O) {
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// First try the generic code, which knows about modifiers like 'c' and 'n'.
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if (!AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O))
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return false;
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0)
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if (ExtraCode[1] != 0)
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return true; // Unknown modifier.
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return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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switch (ExtraCode[0]) {
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default:
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// See if this is a generic print operand
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return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
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case 'r':
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case 'r':
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break;
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break;
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default:
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return true;
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}
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}
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}
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}
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AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
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// TODO: Should be able to support other operand types like globals.
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*TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());
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const MachineOperand &MO = MI->getOperand(OpNo);
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return false;
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if (MO.isReg()) {
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AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
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*MF->getSubtarget().getRegisterInfo());
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return false;
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}
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return true;
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}
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}
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@ -246,3 +246,19 @@ entry:
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store i32 %add, i32 addrspace(1)* undef
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store i32 %add, i32 addrspace(1)* undef
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ret void
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ret void
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}
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}
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; CHECK-LABEL: {{^}}asm_constraint_c_n:
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; CHECK: s_trap 10{{$}}
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define amdgpu_kernel void @asm_constraint_c_n() {
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entry:
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tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1
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ret void
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}
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; CHECK-LABEL: {{^}}asm_constraint_n_n:
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; CHECK: s_trap -10{{$}}
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define amdgpu_kernel void @asm_constraint_n_n() {
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entry:
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tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
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ret void
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}
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