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AMDGPU/SI: Promote i16 = fp_[us]int f32 for VI
Summary: This fixes a regression caused by r286464. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D26570 llvm-svn: 286687
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@ -271,6 +271,12 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
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setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
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AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
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setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
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AddPromotedToType(ISD::FP_TO_SINT, MVT::i16, MVT::i32);
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setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
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AddPromotedToType(ISD::FP_TO_UINT, MVT::i16, MVT::i32);
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}
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setTargetDAGCombine(ISD::FADD);
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@ -248,5 +248,14 @@ define void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_f32_i16:
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; SI: v_cvt_i32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; SI: buffer_store_short [[VAL]]
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define void @fp_to_sint_f32_i16(i16 addrspace(1)* %out, float %in) #0 {
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%sint = fptosi float %in to i16
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store i16 %sint, i16 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,FUNC,SI
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,FUNC,VI
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=EG -check-prefix=FUNC
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declare float @llvm.fabs.f32(float) #1
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@ -7,8 +7,8 @@ declare float @llvm.fabs.f32(float) #1
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; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i32:
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: v_cvt_u32_f32_e32
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; SI: s_endpgm
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; GCN: v_cvt_u32_f32_e32
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; GCN: s_endpgm
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define void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
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%conv = fptoui float %in to i32
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store i32 %conv, i32 addrspace(1)* %out
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@ -19,8 +19,8 @@ define void @fp_to_uint_f32_to_i32 (i32 addrspace(1)* %out, float %in) {
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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define void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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%result = fptoui <2 x float> %in to <2 x i32>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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@ -32,10 +32,10 @@ define void @fp_to_uint_v2f32_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x float>
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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; SI: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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define void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float>, <4 x float> addrspace(1) * %in
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@ -67,7 +67,7 @@ define void @fp_to_uint_v4f32_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x float>
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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; GCN: s_endpgm
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define void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
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%conv = fptoui float %x to i64
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store i64 %conv, i64 addrspace(1)* %out
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@ -118,7 +118,7 @@ define void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %x) {
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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; GCN: s_endpgm
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define void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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%conv = fptoui <2 x float> %x to <2 x i64>
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store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
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@ -211,7 +211,7 @@ define void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x float>
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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; GCN: s_endpgm
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define void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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%conv = fptoui <4 x float> %x to <4 x i64>
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store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
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@ -220,7 +220,7 @@ define void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x float>
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; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i1:
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; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
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; GCN: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
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; EG: AND_INT
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; EG: SETE_DX10 {{[*]?}} T{{[0-9]+}}.{{[XYZW]}}, KC0[2].Z, 1.0,
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@ -231,7 +231,7 @@ define void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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}
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; FUNC-LABEL: {{^}}fp_to_uint_fabs_f32_to_i1:
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; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, |s{{[0-9]+}}|
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; GCN: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, |s{{[0-9]+}}|
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define void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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%in.fabs = call float @llvm.fabs.f32(float %in)
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%conv = fptoui float %in.fabs to i1
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@ -239,5 +239,18 @@ define void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i16:
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; The reason different instructions are used on SI and VI is because for
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; SI fp_to_uint is legalized by the type legalizer and for VI it is
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; legalized by the dag legalizer and they legalize fp_to_uint differently.
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; SI: v_cvt_u32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; VI: v_cvt_i32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; GCN: buffer_store_short [[VAL]]
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define void @fp_to_uint_f32_to_i16(i16 addrspace(1)* %out, float %in) #0 {
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%uint = fptoui float %in to i16
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store i16 %uint, i16 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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