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add the FPBinOp class
llvm-svn: 30980
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@ -51,6 +51,11 @@ class IntBinOp<string OpcStr, SDNode OpNode> :
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
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class FPBinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
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class Addr1BinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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@ -251,17 +256,13 @@ def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
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// Floating Point Arithmetic
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def FADDS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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"fadds $dst, $a, $b",
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[(set FPRegs:$dst, (fadd FPRegs:$a, FPRegs:$b))]>;
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def FADDS : FPBinOp<"fadds", fadd>;
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def FADDD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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"faddd $dst, $a, $b",
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[(set DFPRegs:$dst, (fadd DFPRegs:$a, DFPRegs:$b))]>;
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def FSUBS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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"fsubs $dst, $a, $b",
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[(set FPRegs:$dst, (fsub FPRegs:$a, FPRegs:$b))]>;
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def FSUBS : FPBinOp<"fsubs", fsub>;
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def FSUBD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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"fsubd $dst, $a, $b",
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@ -275,9 +276,7 @@ def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
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"fnegd $dst, $src",
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[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
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def FMULS : InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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"fmuls $dst, $a, $b",
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[(set FPRegs:$dst, (fmul FPRegs:$a, FPRegs:$b))]>;
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def FMULS : FPBinOp<"fmuls", fmul>;
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def FMULD : InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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"fmuld $dst, $a, $b",
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