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[PowerPC] Implement low-order Vector Multiply, Modulus and Divide Instructions
This patch aims to implement the low order vector multiply, divide and modulo instructions available on Power10. The patch involves legalizing the ISD nodes MUL, UDIV, SDIV, UREM and SREM for v2i64 and v4i32 vector types in order to utilize the following instructions: - Vector Multiply Low Doubleword: vmulld - Vector Modulus Word/Doubleword: vmodsw, vmoduw, vmodsd, vmodud - Vector Divide Word/Doubleword: vdivsw, vdivsd, vdivuw, vdivud Differential Revision: https://reviews.llvm.org/D82510
This commit is contained in:
Amy Kwan
parent
cb35cea843
commit
57e04066c4
@ -809,6 +809,18 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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else
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setOperationAction(ISD::MUL, MVT::v4i32, Custom);
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if (Subtarget.isISA3_1()) {
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setOperationAction(ISD::MUL, MVT::v2i64, Legal);
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setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
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setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
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setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
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setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
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setOperationAction(ISD::UREM, MVT::v2i64, Legal);
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setOperationAction(ISD::SREM, MVT::v2i64, Legal);
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setOperationAction(ISD::UREM, MVT::v4i32, Legal);
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setOperationAction(ISD::SREM, MVT::v4i32, Legal);
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}
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setOperationAction(ISD::MUL, MVT::v8i16, Legal);
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setOperationAction(ISD::MUL, MVT::v16i8, Custom);
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@ -973,7 +973,8 @@ let Predicates = [IsISA3_1] in {
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[(set v16i8:$vD,
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(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
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def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulld $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vmulld $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>;
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def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulhsw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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@ -983,21 +984,29 @@ let Predicates = [IsISA3_1] in {
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def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulhud $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmodsw $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vmodsw $vD, $vA, $vB", IIC_VecGeneral,
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[(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>;
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def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmoduw $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vmoduw $vD, $vA, $vB", IIC_VecGeneral,
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[(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>;
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def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmodsd $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vmodsd $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>;
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def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmodud $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vmodud $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>;
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def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivsw $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vdivsw $vD, $vA, $vB", IIC_VecGeneral,
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[(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>;
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def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivuw $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vdivuw $vD, $vA, $vB", IIC_VecGeneral,
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[(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>;
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def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivsd $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vdivsd $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>;
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def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivud $vD, $vA, $vB", IIC_VecGeneral, []>;
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"vdivud $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>;
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def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivesw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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51
test/CodeGen/PowerPC/p10-vector-divide.ll
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51
test/CodeGen/PowerPC/p10-vector-divide.ll
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@ -0,0 +1,51 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector divide instructions on Power10.
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; This includes the low order and extended versions of vector divide,
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; that operate on signed and unsigned words and doublewords.
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define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivud:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivud v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = udiv <2 x i64> %a, %b
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ret <2 x i64> %div
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}
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define <2 x i64> @test_vdivsd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vdivsd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivsd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = sdiv <2 x i64> %a, %b
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ret <2 x i64> %div
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}
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define <4 x i32> @test_vdivuw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivuw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = udiv <4 x i32> %a, %b
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ret <4 x i32> %div
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}
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define <4 x i32> @test_vdivsw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vdivsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdivsw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%div = sdiv <4 x i32> %a, %b
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ret <4 x i32> %div
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}
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107
test/CodeGen/PowerPC/p10-vector-modulo.ll
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107
test/CodeGen/PowerPC/p10-vector-modulo.ll
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@ -0,0 +1,107 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector modulo instructions on Power10.
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; The vector modulo instructions operate on signed and unsigned words
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; and doublewords.
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define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmodud:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmodud v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = urem <2 x i64> %a, %b
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ret <2 x i64> %rem
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}
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define <2 x i64> @test_vmodsd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmodsd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmodsd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = srem <2 x i64> %a, %b
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ret <2 x i64> %rem
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}
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define <4 x i32> @test_vmoduw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vmoduw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmoduw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = urem <4 x i32> %a, %b
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ret <4 x i32> %rem
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}
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define <4 x i32> @test_vmodsw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vmodsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmodsw v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = srem <4 x i32> %a, %b
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ret <4 x i32> %rem
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}
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define <2 x i64> @test_vmodud_with_div(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmodud_with_div:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmodud v4, v2, v3
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; CHECK-NEXT: vdivud v2, v2, v3
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; CHECK-NEXT: vaddudm v2, v4, v2
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; CHECK-NEXT: blr
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entry:
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%rem = urem <2 x i64> %a, %b
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%div = udiv <2 x i64> %a, %b
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%add = add <2 x i64> %rem, %div
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ret <2 x i64> %add
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}
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define <2 x i64> @test_vmodsd_with_div(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmodsd_with_div:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmodsd v4, v2, v3
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; CHECK-NEXT: vdivsd v2, v2, v3
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; CHECK-NEXT: vaddudm v2, v4, v2
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; CHECK-NEXT: blr
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entry:
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%rem = srem <2 x i64> %a, %b
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%div = sdiv <2 x i64> %a, %b
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%add = add <2 x i64> %rem, %div
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ret <2 x i64> %add
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}
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define <4 x i32> @test_vmoduw_with_div(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vmoduw_with_div:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmoduw v4, v2, v3
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; CHECK-NEXT: vdivuw v2, v2, v3
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; CHECK-NEXT: vadduwm v2, v4, v2
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; CHECK-NEXT: blr
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entry:
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%rem = urem <4 x i32> %a, %b
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%div = udiv <4 x i32> %a, %b
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%add = add <4 x i32> %rem, %div
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ret <4 x i32> %add
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}
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define <4 x i32> @test_vmodsw_div(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vmodsw_div:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmodsw v4, v2, v3
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; CHECK-NEXT: vdivsw v2, v2, v3
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; CHECK-NEXT: vadduwm v2, v4, v2
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; CHECK-NEXT: blr
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entry:
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%rem = srem <4 x i32> %a, %b
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%div = sdiv <4 x i32> %a, %b
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%add = add <4 x i32> %rem, %div
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ret <4 x i32> %add
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}
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19
test/CodeGen/PowerPC/p10-vector-multiply.ll
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19
test/CodeGen/PowerPC/p10-vector-multiply.ll
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@ -0,0 +1,19 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector multiply instructions on Power10.
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define <2 x i64> @test_vmulld(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmulld:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmulld v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%mul = mul <2 x i64> %b, %a
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ret <2 x i64> %mul
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}
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