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Add an easy microoptimization I noticed.
llvm-svn: 43164
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@ -573,3 +573,22 @@ __Z11no_overflowjj:
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bx lr
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//===---------------------------------------------------------------------===//
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Easy ARM microoptimization (with -mattr=+vfp2):
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define i64 @i(double %X) {
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%Y = bitcast double %X to i64
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ret i64 %Y
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}
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compiles into:
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_i:
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fmdrr d0, r0, r1
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fmrrd r0, r1, d0
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bx lr
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This just needs a target-specific dag combine to merge the two ARMISD nodes.
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//===---------------------------------------------------------------------===//
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