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When generating spill and reload code for vector registers on PowerPC,

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the compiler makes use of GPR0.  However, there are two flavors of
GPR0 defined by the target:  the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0).  The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.

This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.

llvm-svn: 165658
This commit is contained in:
Bill Schmidt 2012-10-10 21:25:01 +00:00
parent 5f0844eeb4
commit 57e3d38632
2 changed files with 31 additions and 6 deletions
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18
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -570,12 +570,15 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
// STVX VAL, 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
bool Is64Bit = TM.getSubtargetImpl()->isPPC64();
unsigned Instr = Is64Bit ? PPC::ADDI8 : PPC::ADDI;
unsigned GPR0 = Is64Bit ? PPC::X0 : PPC::R0;
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Instr), GPR0),
FrameIdx, 0, 0));
NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
.addReg(SrcReg, getKillRegState(isKill))
.addReg(PPC::R0)
.addReg(PPC::R0));
.addReg(GPR0)
.addReg(GPR0));
} else {
llvm_unreachable("Unknown regclass!");
}
@ -707,10 +710,13 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
// Dest = LVX 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
bool Is64Bit = TM.getSubtargetImpl()->isPPC64();
unsigned Instr = Is64Bit ? PPC::ADDI8 : PPC::ADDI;
unsigned GPR0 = Is64Bit ? PPC::X0 : PPC::R0;
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Instr), GPR0),
FrameIdx, 0, 0));
NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
.addReg(PPC::R0));
NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(GPR0)
.addReg(GPR0));
} else {
llvm_unreachable("Unknown regclass!");
}

19
test/CodeGen/PowerPC/vrspill.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
; This verifies that we generate correct spill/reload code for vector regs.
define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
entry:
%i.addr = alloca i32, align 4
%w.addr = alloca <4 x float>, align 16
store i32 %i, i32* %i.addr, align 4
store <4 x float> %w, <4 x float>* %w.addr, align 16
call void @foo(i32* %i.addr)
ret void
}
; CHECK: stvx 2, 0, 0
; CHECK: lvx 2, 0, 0
declare void @foo(i32*)