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[ARM] Look through concat when lowering in-place shuffles (VZIP, ..)
Currently, we canonicalize shuffles that produce a result larger than their operands with: shuffle(concat(v1, undef), concat(v2, undef)) -> shuffle(concat(v1, v2), undef) because we can access quad vectors (see PerformVECTOR_SHUFFLECombine). This is useful in the general case, but there are special cases where native shuffles produce larger results: the two-result ops. We can look through the concat when lowering them: shuffle(concat(v1, v2), undef) -> concat(VZIP(v1, v2):0, :1) This lets us generate the native shuffles instead of scalarizing to dozens of VMOVs. Differential Revision: http://reviews.llvm.org/D10424 llvm-svn: 240118
This commit is contained in:
Ahmed Bougacha
parent
d492dfd93e
commit
57ebe7191c
@ -5715,6 +5715,44 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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.getValue(WhichResult);
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}
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// Also check for these shuffles through CONCAT_VECTORS: we canonicalize
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// shuffles that produce a result larger than their operands with:
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// shuffle(concat(v1, undef), concat(v2, undef))
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// ->
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// shuffle(concat(v1, v2), undef)
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// because we can access quad vectors (see PerformVECTOR_SHUFFLECombine).
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//
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// This is useful in the general case, but there are special cases where
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// native shuffles produce larger results: the two-result ops.
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//
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// Look through the concat when lowering them:
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// shuffle(concat(v1, v2), undef)
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// ->
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// concat(VZIP(v1, v2):0, :1)
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//
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if (V1->getOpcode() == ISD::CONCAT_VECTORS &&
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V2->getOpcode() == ISD::UNDEF) {
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SDValue SubV1 = V1->getOperand(0);
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SDValue SubV2 = V1->getOperand(1);
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EVT SubVT = SubV1.getValueType();
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// We expect these to have been canonicalized to -1.
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assert(std::all_of(ShuffleMask.begin(), ShuffleMask.end(), [&](int i) {
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return i < (int)VT.getVectorNumElements();
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}) && "Unexpected shuffle index into UNDEF operand!");
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if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
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ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
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if (isV_UNDEF)
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SubV2 = SubV1;
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assert((WhichResult == 0) &&
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"In-place shuffle of concat can only have one result!");
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SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
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SubV1, SubV2);
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
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Res.getValue(1));
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}
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}
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}
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// If the shuffle is not directly supported and it has 4 elements, use
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@ -20,40 +20,9 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrni8_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d19, [r0]
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; CHECK-NEXT: vldr d18, [r1]
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; CHECK-NEXT: vmov.u8 r0, d19[0]
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; CHECK-NEXT: vmov.8 d16[0], r0
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; CHECK-NEXT: vmov.u8 r0, d18[0]
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; CHECK-NEXT: vmov.8 d16[1], r0
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; CHECK-NEXT: vmov.u8 r0, d19[2]
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; CHECK-NEXT: vmov.8 d16[2], r0
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; CHECK-NEXT: vmov.u8 r0, d18[2]
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; CHECK-NEXT: vmov.8 d16[3], r0
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; CHECK-NEXT: vmov.u8 r0, d19[4]
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; CHECK-NEXT: vmov.8 d16[4], r0
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; CHECK-NEXT: vmov.u8 r0, d18[4]
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; CHECK-NEXT: vmov.8 d16[5], r0
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; CHECK-NEXT: vmov.u8 r0, d19[6]
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; CHECK-NEXT: vmov.8 d16[6], r0
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; CHECK-NEXT: vmov.u8 r0, d18[6]
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; CHECK-NEXT: vmov.8 d16[7], r0
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; CHECK-NEXT: vmov.u8 r0, d19[1]
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; CHECK-NEXT: vmov.8 d17[0], r0
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; CHECK-NEXT: vmov.u8 r0, d18[1]
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; CHECK-NEXT: vmov.8 d17[1], r0
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; CHECK-NEXT: vmov.u8 r0, d19[3]
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; CHECK-NEXT: vmov.8 d17[2], r0
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; CHECK-NEXT: vmov.u8 r0, d18[3]
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; CHECK-NEXT: vmov.8 d17[3], r0
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; CHECK-NEXT: vmov.u8 r0, d19[5]
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; CHECK-NEXT: vmov.8 d17[4], r0
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; CHECK-NEXT: vmov.u8 r0, d18[5]
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; CHECK-NEXT: vmov.8 d17[5], r0
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; CHECK-NEXT: vmov.u8 r0, d19[7]
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; CHECK-NEXT: vmov.8 d17[6], r0
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; CHECK-NEXT: vmov.u8 r0, d18[7]
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; CHECK-NEXT: vmov.8 d17[7], r0
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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@ -83,26 +52,11 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vtrni16_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vmov.u16 r0, d16[0]
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; CHECK-NEXT: vmov.16 d18[0], r0
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; CHECK-NEXT: vmov.u16 r0, d17[0]
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; CHECK-NEXT: vmov.16 d18[1], r0
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; CHECK-NEXT: vmov.u16 r0, d16[2]
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; CHECK-NEXT: vmov.16 d18[2], r0
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; CHECK-NEXT: vmov.u16 r0, d17[2]
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; CHECK-NEXT: vmov.16 d18[3], r0
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; CHECK-NEXT: vmov.u16 r0, d16[1]
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; CHECK-NEXT: vmov.16 d19[0], r0
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; CHECK-NEXT: vmov.u16 r0, d17[1]
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; CHECK-NEXT: vmov.16 d19[1], r0
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; CHECK-NEXT: vmov.u16 r0, d16[3]
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; CHECK-NEXT: vmov.16 d19[2], r0
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; CHECK-NEXT: vmov.u16 r0, d17[3]
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; CHECK-NEXT: vmov.16 d19[3], r0
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; CHECK-NEXT: vmov r0, r1, d18
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; CHECK-NEXT: vmov r2, r3, d19
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.16 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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@ -132,8 +86,7 @@ define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.32 q9, q8
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; CHECK-NEXT: vuzp.32 q8, q9
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; CHECK-NEXT: vtrn.32 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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@ -165,8 +118,7 @@ define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vrev64.32 q9, q8
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; CHECK-NEXT: vuzp.32 q8, q9
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; CHECK-NEXT: vtrn.32 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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@ -329,32 +281,9 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrni8_undef_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d18, [r0]
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; CHECK-NEXT: vldr d19, [r1]
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; CHECK-NEXT: vmov.u8 r0, d18[0]
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; CHECK-NEXT: vmov.8 d16[0], r0
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; CHECK-NEXT: vmov.u8 r0, d18[2]
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; CHECK-NEXT: vmov.8 d16[2], r0
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; CHECK-NEXT: vmov.u8 r0, d19[2]
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; CHECK-NEXT: vmov.8 d16[3], r0
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; CHECK-NEXT: vmov.u8 r0, d19[4]
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; CHECK-NEXT: vmov.8 d16[5], r0
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; CHECK-NEXT: vmov.u8 r0, d18[6]
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; CHECK-NEXT: vmov.8 d16[6], r0
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; CHECK-NEXT: vmov.u8 r0, d19[6]
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; CHECK-NEXT: vmov.8 d16[7], r0
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; CHECK-NEXT: vmov.u8 r0, d18[1]
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; CHECK-NEXT: vmov.8 d17[0], r0
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; CHECK-NEXT: vmov.u8 r0, d19[1]
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; CHECK-NEXT: vmov.8 d17[1], r0
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; CHECK-NEXT: vmov.u8 r0, d18[3]
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; CHECK-NEXT: vmov.8 d17[2], r0
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; CHECK-NEXT: vmov.u8 r0, d19[3]
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; CHECK-NEXT: vmov.8 d17[3], r0
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; CHECK-NEXT: vmov.u8 r0, d18[5]
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; CHECK-NEXT: vmov.8 d17[4], r0
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; CHECK-NEXT: vmov.u8 r0, d19[7]
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; CHECK-NEXT: vmov.8 d17[7], r0
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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@ -20,40 +20,9 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpi8_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d19, [r0]
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; CHECK-NEXT: vldr d18, [r1]
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; CHECK-NEXT: vmov.u8 r0, d19[0]
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; CHECK-NEXT: vmov.8 d16[0], r0
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; CHECK-NEXT: vmov.u8 r0, d19[2]
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; CHECK-NEXT: vmov.8 d16[1], r0
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; CHECK-NEXT: vmov.u8 r0, d19[4]
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; CHECK-NEXT: vmov.8 d16[2], r0
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; CHECK-NEXT: vmov.u8 r0, d19[6]
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; CHECK-NEXT: vmov.8 d16[3], r0
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; CHECK-NEXT: vmov.u8 r0, d18[0]
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; CHECK-NEXT: vmov.8 d16[4], r0
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; CHECK-NEXT: vmov.u8 r0, d18[2]
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; CHECK-NEXT: vmov.8 d16[5], r0
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; CHECK-NEXT: vmov.u8 r0, d18[4]
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; CHECK-NEXT: vmov.8 d16[6], r0
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; CHECK-NEXT: vmov.u8 r0, d18[6]
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; CHECK-NEXT: vmov.8 d16[7], r0
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; CHECK-NEXT: vmov.u8 r0, d19[1]
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; CHECK-NEXT: vmov.8 d17[0], r0
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; CHECK-NEXT: vmov.u8 r0, d19[3]
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; CHECK-NEXT: vmov.8 d17[1], r0
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; CHECK-NEXT: vmov.u8 r0, d19[5]
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; CHECK-NEXT: vmov.8 d17[2], r0
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; CHECK-NEXT: vmov.u8 r0, d19[7]
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; CHECK-NEXT: vmov.8 d17[3], r0
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; CHECK-NEXT: vmov.u8 r0, d18[1]
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; CHECK-NEXT: vmov.8 d17[4], r0
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; CHECK-NEXT: vmov.u8 r0, d18[3]
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; CHECK-NEXT: vmov.8 d17[5], r0
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; CHECK-NEXT: vmov.u8 r0, d18[5]
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; CHECK-NEXT: vmov.8 d17[6], r0
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; CHECK-NEXT: vmov.u8 r0, d18[7]
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; CHECK-NEXT: vmov.8 d17[7], r0
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vuzp.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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@ -83,26 +52,11 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vuzpi16_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vmov.u16 r0, d16[0]
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; CHECK-NEXT: vmov.16 d18[0], r0
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; CHECK-NEXT: vmov.u16 r0, d16[2]
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; CHECK-NEXT: vmov.16 d18[1], r0
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; CHECK-NEXT: vmov.u16 r0, d17[0]
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; CHECK-NEXT: vmov.16 d18[2], r0
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; CHECK-NEXT: vmov.u16 r0, d17[2]
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; CHECK-NEXT: vmov.16 d18[3], r0
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; CHECK-NEXT: vmov.u16 r0, d16[1]
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; CHECK-NEXT: vmov.16 d19[0], r0
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; CHECK-NEXT: vmov.u16 r0, d16[3]
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; CHECK-NEXT: vmov.16 d19[1], r0
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; CHECK-NEXT: vmov.u16 r0, d17[1]
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; CHECK-NEXT: vmov.16 d19[2], r0
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; CHECK-NEXT: vmov.u16 r0, d17[3]
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; CHECK-NEXT: vmov.16 d19[3], r0
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; CHECK-NEXT: vmov r0, r1, d18
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; CHECK-NEXT: vmov r2, r3, d19
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vuzp.16 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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@ -266,32 +220,9 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vuzpi8_undef_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d18, [r0]
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; CHECK-NEXT: vldr d19, [r1]
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; CHECK-NEXT: vmov.u8 r0, d18[0]
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; CHECK-NEXT: vmov.8 d16[0], r0
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; CHECK-NEXT: vmov.u8 r0, d18[2]
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; CHECK-NEXT: vmov.8 d16[1], r0
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; CHECK-NEXT: vmov.u8 r0, d19[0]
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; CHECK-NEXT: vmov.8 d16[4], r0
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; CHECK-NEXT: vmov.u8 r0, d19[2]
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; CHECK-NEXT: vmov.8 d16[5], r0
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; CHECK-NEXT: vmov.u8 r0, d19[4]
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; CHECK-NEXT: vmov.8 d16[6], r0
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; CHECK-NEXT: vmov.u8 r0, d19[6]
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; CHECK-NEXT: vmov.8 d16[7], r0
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; CHECK-NEXT: vmov.u8 r0, d18[1]
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; CHECK-NEXT: vmov.8 d17[0], r0
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; CHECK-NEXT: vmov.u8 r0, d18[3]
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; CHECK-NEXT: vmov.8 d17[1], r0
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; CHECK-NEXT: vmov.u8 r0, d18[5]
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; CHECK-NEXT: vmov.8 d17[2], r0
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; CHECK-NEXT: vmov.u8 r0, d18[7]
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; CHECK-NEXT: vmov.8 d17[3], r0
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; CHECK-NEXT: vmov.u8 r0, d19[5]
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; CHECK-NEXT: vmov.8 d17[6], r0
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; CHECK-NEXT: vmov.u8 r0, d19[7]
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; CHECK-NEXT: vmov.8 d17[7], r0
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vuzp.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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@ -20,40 +20,9 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vzipi8_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d19, [r0]
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; CHECK-NEXT: vldr d18, [r1]
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; CHECK-NEXT: vmov.u8 r0, d19[0]
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; CHECK-NEXT: vmov.8 d16[0], r0
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; CHECK-NEXT: vmov.u8 r0, d18[0]
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; CHECK-NEXT: vmov.8 d16[1], r0
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; CHECK-NEXT: vmov.u8 r0, d19[1]
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; CHECK-NEXT: vmov.8 d16[2], r0
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; CHECK-NEXT: vmov.u8 r0, d18[1]
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; CHECK-NEXT: vmov.8 d16[3], r0
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; CHECK-NEXT: vmov.u8 r0, d19[2]
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; CHECK-NEXT: vmov.8 d16[4], r0
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; CHECK-NEXT: vmov.u8 r0, d18[2]
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; CHECK-NEXT: vmov.8 d16[5], r0
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; CHECK-NEXT: vmov.u8 r0, d19[3]
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; CHECK-NEXT: vmov.8 d16[6], r0
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; CHECK-NEXT: vmov.u8 r0, d18[3]
|
||||
; CHECK-NEXT: vmov.8 d16[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[4]
|
||||
; CHECK-NEXT: vmov.8 d17[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[4]
|
||||
; CHECK-NEXT: vmov.8 d17[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[5]
|
||||
; CHECK-NEXT: vmov.8 d17[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[5]
|
||||
; CHECK-NEXT: vmov.8 d17[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[6]
|
||||
; CHECK-NEXT: vmov.8 d17[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[6]
|
||||
; CHECK-NEXT: vmov.8 d17[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[7]
|
||||
; CHECK-NEXT: vmov.8 d17[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[7]
|
||||
; CHECK-NEXT: vmov.8 d17[7], r0
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vzip.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
@ -83,26 +52,11 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
; CHECK-LABEL: vzipi16_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vmov.u16 r0, d16[0]
|
||||
; CHECK-NEXT: vmov.16 d18[0], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d17[0]
|
||||
; CHECK-NEXT: vmov.16 d18[1], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d16[1]
|
||||
; CHECK-NEXT: vmov.16 d18[2], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d17[1]
|
||||
; CHECK-NEXT: vmov.16 d18[3], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d16[2]
|
||||
; CHECK-NEXT: vmov.16 d19[0], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d17[2]
|
||||
; CHECK-NEXT: vmov.16 d19[1], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d16[3]
|
||||
; CHECK-NEXT: vmov.16 d19[2], r0
|
||||
; CHECK-NEXT: vmov.u16 r0, d17[3]
|
||||
; CHECK-NEXT: vmov.16 d19[3], r0
|
||||
; CHECK-NEXT: vmov r0, r1, d18
|
||||
; CHECK-NEXT: vmov r2, r3, d19
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vzip.16 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>, <4 x i16>* %B
|
||||
@ -266,32 +220,9 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vzipi8_undef_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d18, [r0]
|
||||
; CHECK-NEXT: vldr d19, [r1]
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[0]
|
||||
; CHECK-NEXT: vmov.8 d16[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[1]
|
||||
; CHECK-NEXT: vmov.8 d16[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[1]
|
||||
; CHECK-NEXT: vmov.8 d16[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[2]
|
||||
; CHECK-NEXT: vmov.8 d16[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[3]
|
||||
; CHECK-NEXT: vmov.8 d16[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[3]
|
||||
; CHECK-NEXT: vmov.8 d16[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[4]
|
||||
; CHECK-NEXT: vmov.8 d17[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[4]
|
||||
; CHECK-NEXT: vmov.8 d17[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[5]
|
||||
; CHECK-NEXT: vmov.8 d17[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[5]
|
||||
; CHECK-NEXT: vmov.8 d17[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d18[6]
|
||||
; CHECK-NEXT: vmov.8 d17[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, d19[7]
|
||||
; CHECK-NEXT: vmov.8 d17[7], r0
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vzip.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user