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[X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.

llvm-svn: 327874
This commit is contained in:
Craig Topper 2018-03-19 17:58:41 +00:00
parent 2523e00d42
commit 58094170aa
5 changed files with 10 additions and 10 deletions

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@ -840,8 +840,8 @@ def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)i")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>;

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@ -1256,8 +1256,8 @@ def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;

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@ -649,8 +649,8 @@ def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)i")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;

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@ -846,8 +846,8 @@ def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;

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@ -1276,8 +1276,8 @@ def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;