RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00
Code Issues Projects Releases Wiki Activity

Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add support to skipping a node."

Browse Source 
Revert accidentally committed change.

This reverts commit r286655.

llvm-svn: 286656
This commit is contained in:
Matthias Braun 2016-11-11 22:39:50 +00:00
parent fc336c30a3
commit 580f8393d4
3 changed files with 3 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -289,7 +289,6 @@ namespace llvm {
bool isCloned : 1; // True if this node has been cloned.
bool isUnbuffered : 1; // Uses an unbuffered resource.
bool hasReservedResource : 1; // Uses a reserved resource.
bool skip : 1; ///< Ignore/Skip this node.
Sched::Preference SchedulingPref; // Scheduling preference.
private:
@ -315,7 +314,7 @@ namespace llvm {
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
isUnbuffered(false), hasReservedResource(false), skip(false),
isUnbuffered(false), hasReservedResource(false),
SchedulingPref(Sched::None), isDepthCurrent(false),
isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
@ -331,7 +330,7 @@ namespace llvm {
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
isUnbuffered(false), hasReservedResource(false), skip(false),
isUnbuffered(false), hasReservedResource(false),
SchedulingPref(Sched::None), isDepthCurrent(false),
isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
@ -346,7 +345,7 @@ namespace llvm {
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
isUnbuffered(false), hasReservedResource(false), skip(false),
isUnbuffered(false), hasReservedResource(false),
SchedulingPref(Sched::None), isDepthCurrent(false),
isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}

7
lib/CodeGen/MachineScheduler.cpp
View File

@ -707,7 +707,6 @@ void ScheduleDAGMI::schedule() {
DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
SUnit *SU = SchedImpl->pickNode(IsTopNode);
if (!SU) break;
assert(!SU->skip);
assert(!SU->isScheduled && "Node already scheduled");
if (!checkSchedLimit())
@ -765,8 +764,6 @@ findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
SmallVectorImpl<SUnit*> &BotRoots) {
for (std::vector<SUnit>::iterator
I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
if (I->skip)
continue;
SUnit *SU = &(*I);
assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
@ -1521,8 +1518,6 @@ void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
SUnit *SU = &DAG->SUnits[Idx];
if (SU->skip)
continue;
if ((IsLoad && !SU->getInstr()->mayLoad()) ||
(!IsLoad && !SU->getInstr()->mayStore()))
continue;
@ -1815,8 +1810,6 @@ void CopyConstrain::apply(ScheduleDAGInstrs *DAGInstrs) {
for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
SUnit *SU = &DAG->SUnits[Idx];
if (SU->skip)
continue;
if (!SU->getInstr()->isCopy())
continue;

4
lib/CodeGen/ScheduleDAG.cpp
View File

@ -329,10 +329,6 @@ void SUnit::dump(const ScheduleDAG *G) const {
void SUnit::dumpAll(const ScheduleDAG *G) const {
dump(G);
if (skip) {
dbgs() << " Skipped\n";
return;
}
dbgs() << " # preds left : " << NumPredsLeft << "\n";
dbgs() << " # succs left : " << NumSuccsLeft << "\n";