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[mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 nodes.
Summary: In order to support big endian targets for the BuildPairF64 nodes we just need to swap the low/high pair registers. Additionally, for the ExtractElementF64 nodes we have to calculate the correct stack offset with respect to the node's register/operand that we want to extract. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5753 llvm-svn: 219931
This commit is contained in:
Vasileios Kalintiris
parent
8d39330886
commit
5822b72dd9
@ -325,6 +325,8 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
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// We re-use the same spill slot each time so that the stack frame doesn't
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// grow too much in functions with a large number of moves.
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int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2);
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if (!Subtarget.isLittle())
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std::swap(LoReg, HiReg);
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TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
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0);
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TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
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@ -369,6 +371,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
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unsigned DstReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned N = I->getOperand(2).getImm();
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int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
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// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
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// the cases where mfhc1 is not available). 64-bit architectures and
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@ -385,7 +388,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
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int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
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TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
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0);
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TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4);
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TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset);
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return true;
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}
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@ -12,9 +12,9 @@
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; this check here.
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-BE
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A-BE
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-LE
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A-LE
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A
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; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A
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; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
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@ -38,15 +38,10 @@ define double @call1(double %d, ...) {
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; 32R2-NO-FP64A-BE: mtc1 $5, $f0
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; 32R2-NO-FP64A-BE: mthc1 $4, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $4, 0($sp)
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; 32R2-FP64A-LE: sw $5, 4($sp)
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; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $5, 0($sp)
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; 32R2-FP64A-BE: sw $4, 4($sp)
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; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
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; 32R2-FP64A: addiu $sp, $sp, -8
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; 32R2-FP64A: sw $4, 0($sp)
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; 32R2-FP64A: sw $5, 4($sp)
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; 32R2-FP64A: ldc1 $f0, 0($sp)
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; 64-NO-FP64A: daddiu $sp, $sp, -64
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; 64-NO-FP64A: mov.d $f0, $f12
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@ -63,15 +58,10 @@ define double @call2(i32 %i, double %d) {
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; 32R2-NO-FP64A-BE: mtc1 $7, $f0
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; 32R2-NO-FP64A-BE: mthc1 $6, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $6, 0($sp)
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; 32R2-FP64A-LE: sw $7, 4($sp)
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; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $7, 0($sp)
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; 32R2-FP64A-BE: sw $6, 4($sp)
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; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
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; 32R2-FP64A: addiu $sp, $sp, -8
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; 32R2-FP64A: sw $6, 0($sp)
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; 32R2-FP64A: sw $7, 4($sp)
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; 32R2-FP64A: ldc1 $f0, 0($sp)
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; 64-NO-FP64A-NOT: daddiu $sp, $sp
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; 64-NO-FP64A: mov.d $f0, $f13
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@ -88,15 +78,10 @@ define double @call3(float %f1, float %f2, double %d) {
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; 32R2-NO-FP64A-BE: mtc1 $7, $f0
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; 32R2-NO-FP64A-BE: mthc1 $6, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $6, 0($sp)
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; 32R2-FP64A-LE: sw $7, 4($sp)
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; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $7, 0($sp)
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; 32R2-FP64A-BE: sw $6, 4($sp)
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; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
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; 32R2-FP64A: addiu $sp, $sp, -8
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; 32R2-FP64A: sw $6, 0($sp)
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; 32R2-FP64A: sw $7, 4($sp)
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; 32R2-FP64A: ldc1 $f0, 0($sp)
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; 64-NO-FP64A-NOT: daddiu $sp, $sp
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; 64-NO-FP64A: mov.d $f0, $f14
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@ -113,15 +98,10 @@ define double @call4(float %f, double %d, ...) {
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; 32R2-NO-FP64A-BE: mtc1 $7, $f0
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; 32R2-NO-FP64A-BE: mthc1 $6, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $6, 0($sp)
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; 32R2-FP64A-LE: sw $7, 4($sp)
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; 32R2-FP64A-LE: ldc1 $f0, 0($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $7, 0($sp)
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; 32R2-FP64A-BE: sw $6, 4($sp)
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; 32R2-FP64A-BE: ldc1 $f0, 0($sp)
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; 32R2-FP64A: addiu $sp, $sp, -8
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; 32R2-FP64A: sw $6, 0($sp)
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; 32R2-FP64A: sw $7, 4($sp)
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; 32R2-FP64A: ldc1 $f0, 0($sp)
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; 64-NO-FP64A: daddiu $sp, $sp, -48
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; 64-NO-FP64A: mov.d $f0, $f13
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@ -145,23 +125,14 @@ define double @call5(double %a, double %b, ...) {
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; 32R2-NO-FP64A-BE-DAG: mthc1 $6, $[[T1:f[0-9]+]]
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; 32R2-NO-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-FP64A-LE: addiu $sp, $sp, -8
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; 32R2-FP64A-LE: sw $6, 0($sp)
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; 32R2-FP64A-LE: sw $7, 4($sp)
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; 32R2-FP64A-LE: ldc1 $[[T1:f[0-9]+]], 0($sp)
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; 32R2-FP64A-LE: sw $4, 0($sp)
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; 32R2-FP64A-LE: sw $5, 4($sp)
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; 32R2-FP64A-LE: ldc1 $[[T0:f[0-9]+]], 0($sp)
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; 32R2-FP64A-LE: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-FP64A-BE: addiu $sp, $sp, -8
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; 32R2-FP64A-BE: sw $7, 0($sp)
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; 32R2-FP64A-BE: sw $6, 4($sp)
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; 32R2-FP64A-BE: ldc1 $[[T1:f[0-9]+]], 0($sp)
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; 32R2-FP64A-BE: sw $5, 0($sp)
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; 32R2-FP64A-BE: sw $4, 4($sp)
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; 32R2-FP64A-BE: ldc1 $[[T0:f[0-9]+]], 0($sp)
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; 32R2-FP64A-BE: sub.d $f0, $[[T0]], $[[T1]]
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; 32R2-FP64A: addiu $sp, $sp, -8
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; 32R2-FP64A: sw $6, 0($sp)
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; 32R2-FP64A: sw $7, 4($sp)
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; 32R2-FP64A: ldc1 $[[T1:f[0-9]+]], 0($sp)
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; 32R2-FP64A: sw $4, 0($sp)
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; 32R2-FP64A: sw $5, 4($sp)
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; 32R2-FP64A: ldc1 $[[T0:f[0-9]+]], 0($sp)
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; 32R2-FP64A: sub.d $f0, $[[T0]], $[[T1]]
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; 64-NO-FP64A: sub.d $f0, $f12, $f13
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}
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@ -179,19 +150,12 @@ define double @move_from(double %d) {
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; 32R2-NO-FP64A-BE-DAG: mfc1 $7, $f0
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; 32R2-NO-FP64A-BE-DAG: mfhc1 $6, $f0
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; 32R2-FP64A-LE: addiu $sp, $sp, -32
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; 32R2-FP64A-LE: sdc1 $f0, 16($sp)
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; 32R2-FP64A-LE: lw $6, 16($sp)
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; 32R2-FP64A: addiu $sp, $sp, -32
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; 32R2-FP64A: sdc1 $f0, 16($sp)
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; 32R2-FP64A: lw $6, 16($sp)
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; FIXME: This store is redundant
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; 32R2-FP64A-LE: sdc1 $f0, 16($sp)
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; 32R2-FP64A-LE: lw $7, 20($sp)
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; 32R2-FP64A-BE: addiu $sp, $sp, -32
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; 32R2-FP64A-BE: sdc1 $f0, 16($sp)
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; 32R2-FP64A-BE: lw $6, 20($sp)
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; FIXME: This store is redundant
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; 32R2-FP64A-BE: sdc1 $f0, 16($sp)
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; 32R2-FP64A-BE: lw $7, 16($sp)
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; 32R2-FP64A: sdc1 $f0, 16($sp)
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; 32R2-FP64A: lw $7, 20($sp)
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; 64-NO-FP64A: mov.d $f13, $f0
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}
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