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[GlobalISel][NFC] Factor out common target code from GlobalISelEmitterTests

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Factor out commonly-used target code from the GlobalISelEmitter tests into
a GlobalISelEmitterCommon.td file. This is tested by the original
GlobalISelEmitter.td test.

This reduces the amount of boilerplate code necessary for tests like this.

Differential Revision: https://reviews.llvm.org/D65777

llvm-svn: 368757
This commit is contained in:
Jessica Paquette 2019-08-13 22:14:37 +00:00
parent ec89908f0e
commit 582c860a72
4 changed files with 26 additions and 47 deletions
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18
test/TableGen/Common/GlobalISelEmitterCommon.td Normal file
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@ -0,0 +1,18 @@
// Common target boilerplate for GlobalISelEmitter tests.
def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; }
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
def GPR32Op : RegisterOperand<GPR32>;
def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
def p0 : PtrValueType <i32, 0>;
class I<dag OOps, dag IOps, list<dag> Pat>
: Instruction {
let Namespace = "MyTarget";
let OutOperandList = OOps;
let InOperandList = IOps;
let Pattern = Pat;
}

9
test/TableGen/GlobalISelEmitter-PR39045.td
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@ -1,4 +1,4 @@
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o %t
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %t
// RUN: FileCheck %s < %t
// Both predicates should be tested
@ -6,9 +6,7 @@
// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a,
include "llvm/Target/Target.td"
def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; }
include "GlobalISelEmitterCommon.td"
def pat_frag_a : PatFrag <(ops node:$ptr), (load node:$ptr), [{}]> {
@ -21,9 +19,6 @@ def pat_frag_b : PatFrag <(ops node:$ptr), (load node:$ptr), [{}]> {
let GISelPredicateCode = [{ return isInstB(MI); }];
}
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
def inst_a : Instruction {
let OutOperandList = (outs GPR32:$dst);
let InOperandList = (ins GPR32:$src);

26
test/TableGen/GlobalISelEmitter.td
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@ -1,6 +1,6 @@
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -optimize-match-table=false %s -o %T/non-optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -optimize-match-table=true %s -o %T/optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o %T/default.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
@ -23,30 +23,14 @@
// RUN: diff %T/default.cpp %T/optimized.cpp
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
//===- Define the necessary boilerplate for our test target. --------------===//
def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; }
let TargetPrefix = "mytarget" in {
def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
}
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
def GPR32Op : RegisterOperand<GPR32>;
def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
class I<dag OOps, dag IOps, list<dag> Pat>
: Instruction {
let Namespace = "MyTarget";
let OutOperandList = OOps;
let InOperandList = IOps;
let Pattern = Pat;
}
def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
let MIOperandInfo = (ops i32imm, i32imm);
}
@ -996,8 +980,6 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
def p0 : PtrValueType <i32, 0>;
def : Pat<(load GPR32:$src),
(p0 (LOAD GPR32:$src))>;

20
test/TableGen/GlobalISelEmitterSkippedPatterns.td
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@ -1,24 +1,8 @@
// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
//===- Boiler plate target code -===//
def MyTargetISA : InstrInfo;
def MyTarget : Target { let InstructionSet = MyTargetISA; }
let TargetPrefix = "mytarget" in {
def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
}
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
class I<dag OOps, dag IOps, list<dag> Pat>
: Instruction {
let Namespace = "MyTarget";
let OutOperandList = OOps;
let InOperandList = IOps;
let Pattern = Pat;
}
def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
let MIOperandInfo = (ops i32imm, i32imm);