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X86: fixup (V)PMADDWD detection

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Fix some bugs (missing checks).
Add constant support.
This commit is contained in:
Nekotekina 2021-05-17 08:18:19 +03:00
parent a7dd06b0f0
commit 5836324d64
1 changed files with 18 additions and 4 deletions
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22
lib/Target/X86/X86ISelLowering.cpp
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@ -41664,9 +41664,11 @@ static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG,
// with zero extends, which should qualify for the optimization.
// Otherwise just fallback to zero-extension check.
if (isa<ConstantSDNode>(N0.getOperand(1).getOperand(0)) &&
N0.getOperand(1).getConstantOperandVal(0) == 16 &&
isa<ConstantSDNode>(N1.getOperand(1).getOperand(0)) &&
N1.getOperand(1).getConstantOperandVal(0) == 16) {
N0.getOperand(1).getConstantOperandVal(0) == 16 &&
N1.getOperand(1).getConstantOperandVal(0) == 16 &&
DAG.isSplatValue(N0.getOperand(1)) &&
DAG.isSplatValue(N1.getOperand(1))) {
// Nullify mask to pass the following check
Mask17 = 0;
N0 = DAG.getNode(ISD::SRL, N0.getNode(), VT, N0.getOperand(0),
@ -41675,8 +41677,20 @@ static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG,
N1.getOperand(1));
}
}
if (!DAG.MaskedValueIsZero(N1, Mask17) ||
!DAG.MaskedValueIsZero(N0, Mask17))
if (!!Mask17 && N0.getOpcode() == ISD::SRA) {
if (isa<ConstantSDNode>(N0.getOperand(1).getOperand(0)) &&
DAG.ComputeNumSignBits(N1) >= 17 &&
DAG.isSplatValue(N0.getOperand(1)) &&
N0.getOperand(1).getConstantOperandVal(0) == 16) {
Mask17 = 0;
N0 = DAG.getNode(ISD::SRL, N0.getNode(), VT, N0.getOperand(0),
N0.getOperand(1));
}
}
if (!!Mask17 && (!DAG.MaskedValueIsZero(N1, Mask17) ||
!DAG.MaskedValueIsZero(N0, Mask17)))
return SDValue();
// Use SplitOpsAndApply to handle AVX splitting.