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https://github.com/RPCS3/llvm-mirror.git
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GISel: Canonicalize select tests using update_mir_test_checks
This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
This commit is contained in:
Justin Bogner
parent
1cd097dca3
commit
58371c32c8
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,4 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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@ -16,248 +17,248 @@
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...
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---
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# CHECK-LABEL: name: bitcast_s32_gpr
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name: bitcast_s32_gpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %w0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: bitcast_s32_gpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr32all
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; CHECK-NEXT: id: 1, class: gpr32all
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; CHECK: [[COPY:%[0-9]+]] = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %w0 = COPY [[COPY1]]
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%0(s32) = COPY %w0
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%1(s32) = G_BITCAST %0
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%w0 = COPY %1(s32)
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...
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---
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# CHECK-LABEL: name: bitcast_s32_fpr
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name: bitcast_s32_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %s0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %s0
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; CHECK-LABEL: name: bitcast_s32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr32
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %s0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %s0 = COPY [[COPY1]]
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%0(s32) = COPY %s0
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%1(s32) = G_BITCAST %0
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%s0 = COPY %1(s32)
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...
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---
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# CHECK-LABEL: name: bitcast_s32_gpr_fpr
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name: bitcast_s32_gpr_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %w0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: bitcast_s32_gpr_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr32all
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %w0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %s0 = COPY [[COPY1]]
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%0(s32) = COPY %w0
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%1(s32) = G_BITCAST %0
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%s0 = COPY %1(s32)
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...
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---
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# CHECK-LABEL: name: bitcast_s32_fpr_gpr
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name: bitcast_s32_fpr_gpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %s0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %s0
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; CHECK-LABEL: name: bitcast_s32_fpr_gpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr32
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; CHECK-NEXT: id: 1, class: gpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %s0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %w0 = COPY [[COPY1]]
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%0(s32) = COPY %s0
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%1(s32) = G_BITCAST %0
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%w0 = COPY %1(s32)
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...
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---
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# CHECK-LABEL: name: bitcast_s64_gpr
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name: bitcast_s64_gpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %x0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: bitcast_s64_gpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr64all
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; CHECK-NEXT: id: 1, class: gpr64all
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; CHECK: [[COPY:%[0-9]+]] = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %x0 = COPY [[COPY1]]
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%0(s64) = COPY %x0
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%1(s64) = G_BITCAST %0
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%x0 = COPY %1(s64)
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...
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---
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# CHECK-LABEL: name: bitcast_s64_fpr
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name: bitcast_s64_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %d0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %d0
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; CHECK-LABEL: name: bitcast_s64_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr64
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %d0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %d0 = COPY [[COPY1]]
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%0(s64) = COPY %d0
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%1(s64) = G_BITCAST %0
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%d0 = COPY %1(s64)
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...
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---
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# CHECK-LABEL: name: bitcast_s64_gpr_fpr
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name: bitcast_s64_gpr_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %x0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: bitcast_s64_gpr_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr64all
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %x0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %d0 = COPY [[COPY1]]
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%0(s64) = COPY %x0
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%1(s64) = G_BITCAST %0
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%d0 = COPY %1(s64)
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...
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---
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# CHECK-LABEL: name: bitcast_s64_fpr_gpr
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name: bitcast_s64_fpr_gpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %d0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %d0
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; CHECK-LABEL: name: bitcast_s64_fpr_gpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr64
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; CHECK-NEXT: id: 1, class: gpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %d0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %x0 = COPY [[COPY1]]
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%0(s64) = COPY %d0
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%1(s64) = G_BITCAST %0
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%x0 = COPY %1(s64)
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...
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---
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# CHECK-LABEL: name: bitcast_s64_v2f32_fpr
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name: bitcast_s64_v2f32_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %d0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %d0
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; CHECK-LABEL: name: bitcast_s64_v2f32_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr64
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %d0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %x0 = COPY [[COPY1]]
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%0(s64) = COPY %d0
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%1(<2 x s32>) = G_BITCAST %0
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%x0 = COPY %1(<2 x s32>)
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...
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---
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# CHECK-LABEL: name: bitcast_s64_v8i8_fpr
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name: bitcast_s64_v8i8_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %d0
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# CHECK: %1 = COPY %0
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body: |
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bb.0:
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liveins: %d0
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; CHECK-LABEL: name: bitcast_s64_v8i8_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr64
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; CHECK-NEXT: id: 1, class: fpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %d0
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; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
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; CHECK: %x0 = COPY [[COPY1]]
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%0(s64) = COPY %d0
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%1(<8 x s8>) = G_BITCAST %0
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%x0 = COPY %1(<8 x s8>)
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@ -1,3 +1,4 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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@ -8,52 +9,50 @@
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...
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---
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# CHECK-LABEL: name: bswap_s32
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name: bswap_s32
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %w0
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# CHECK: %1 = REVWr %0
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# CHECK: %w0 = COPY %1
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body: |
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bb.0:
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liveins: %w0
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; CHECK-LABEL: name: bswap_s32
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr32
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; CHECK-NEXT: id: 1, class: gpr32
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; CHECK: [[COPY:%[0-9]+]] = COPY %w0
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; CHECK: [[REVWr:%[0-9]+]] = REVWr [[COPY]]
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; CHECK: %w0 = COPY [[REVWr]]
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%0(s32) = COPY %w0
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%1(s32) = G_BSWAP %0
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%w0 = COPY %1
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...
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---
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# CHECK-LABEL: name: bswap_s64
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name: bswap_s64
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %x0
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# CHECK: %1 = REVXr %0
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# CHECK: %x0 = COPY %1
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body: |
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bb.0:
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liveins: %x0
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; CHECK-LABEL: name: bswap_s64
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: gpr64
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; CHECK-NEXT: id: 1, class: gpr64
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; CHECK: [[COPY:%[0-9]+]] = COPY %x0
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; CHECK: [[REVXr:%[0-9]+]] = REVXr [[COPY]]
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; CHECK: %x0 = COPY [[REVXr]]
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%0(s64) = COPY %x0
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%1(s64) = G_BSWAP %0
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%x0 = COPY %1
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@ -1,3 +1,4 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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@ -7,31 +8,31 @@
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...
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---
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# CHECK-LABEL: name: FMADDSrrr_fpr
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name: FMADDSrrr_fpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
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# CHECK-NEXT: - { id: 3, class: fpr32, preferred-register: '' }
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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# CHECK: body:
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# CHECK: %0 = COPY %w0
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# CHECK: %1 = COPY %w1
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# CHECK: %2 = COPY %w2
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# CHECK: %3 = FMADDSrrr %0, %1, %2
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body: |
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bb.0:
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liveins: %w0, %w1, %w2
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; CHECK-LABEL: name: FMADDSrrr_fpr
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; CHECK: registers:
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; CHECK-NEXT: id: 0, class: fpr32
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; CHECK-NEXT: id: 1, class: fpr32
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; CHECK-NEXT: id: 2, class: fpr32
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; CHECK-NEXT: id: 3, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: [[COPY2:%[0-9]+]] = COPY %w2
|
||||
; CHECK: [[FMADDSrrr:%[0-9]+]] = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
|
||||
; CHECK: %x0 = COPY [[FMADDSrrr]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s32) = COPY %w1
|
||||
%2(s32) = COPY %w2
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -33,550 +34,550 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptrunc_s16_s32_fpr
|
||||
name: fptrunc_s16_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK: - { id: 0, class: fpr32, preferred-register: '' }
|
||||
# CHECK: - { id: 1, class: fpr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %s0
|
||||
# CHECK: %1 = FCVTHSr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %s0
|
||||
|
||||
; CHECK-LABEL: name: fptrunc_s16_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr32
|
||||
; CHECK-NEXT: id: 1, class: fpr16
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
||||
; CHECK: [[FCVTHSr:%[0-9]+]] = FCVTHSr [[COPY]]
|
||||
; CHECK: %h0 = COPY [[FCVTHSr]]
|
||||
%0(s32) = COPY %s0
|
||||
%1(s16) = G_FPTRUNC %0
|
||||
%h0 = COPY %1(s16)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptrunc_s16_s64_fpr
|
||||
name: fptrunc_s16_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK: - { id: 1, class: fpr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %1 = FCVTHDr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fptrunc_s16_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: fpr16
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[FCVTHDr:%[0-9]+]] = FCVTHDr [[COPY]]
|
||||
; CHECK: %h0 = COPY [[FCVTHDr]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s16) = G_FPTRUNC %0
|
||||
%h0 = COPY %1(s16)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptrunc_s32_s64_fpr
|
||||
name: fptrunc_s32_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %1 = FCVTSDr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fptrunc_s32_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[FCVTSDr:%[0-9]+]] = FCVTSDr [[COPY]]
|
||||
; CHECK: %s0 = COPY [[FCVTSDr]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s32) = G_FPTRUNC %0
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fpext_s32_s16_fpr
|
||||
name: fpext_s32_s16_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK: - { id: 0, class: fpr16, preferred-register: '' }
|
||||
# CHECK: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %h0
|
||||
# CHECK: %1 = FCVTSHr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %h0
|
||||
|
||||
; CHECK-LABEL: name: fpext_s32_s16_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr16
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %h0
|
||||
; CHECK: [[FCVTSHr:%[0-9]+]] = FCVTSHr [[COPY]]
|
||||
; CHECK: %s0 = COPY [[FCVTSHr]]
|
||||
%0(s16) = COPY %h0
|
||||
%1(s32) = G_FPEXT %0
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fpext_s64_s16_fpr
|
||||
name: fpext_s64_s16_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK: - { id: 0, class: fpr16, preferred-register: '' }
|
||||
# CHECK: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %h0
|
||||
# CHECK: %1 = FCVTDHr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %h0
|
||||
|
||||
; CHECK-LABEL: name: fpext_s64_s16_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr16
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %h0
|
||||
; CHECK: [[FCVTDHr:%[0-9]+]] = FCVTDHr [[COPY]]
|
||||
; CHECK: %d0 = COPY [[FCVTDHr]]
|
||||
%0(s16) = COPY %h0
|
||||
%1(s64) = G_FPEXT %0
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fpext_s64_s32_fpr
|
||||
name: fpext_s64_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK: - { id: 0, class: fpr32, preferred-register: '' }
|
||||
# CHECK: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %s0
|
||||
# CHECK: %1 = FCVTDSr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fpext_s64_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr32
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
||||
; CHECK: [[FCVTDSr:%[0-9]+]] = FCVTDSr [[COPY]]
|
||||
; CHECK: %d0 = COPY [[FCVTDSr]]
|
||||
%0(s32) = COPY %s0
|
||||
%1(s64) = G_FPEXT %0
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sitofp_s32_s32_fpr
|
||||
name: sitofp_s32_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = SCVTFUWSri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: sitofp_s32_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SCVTFUWSri:%[0-9]+]] = SCVTFUWSri [[COPY]]
|
||||
; CHECK: %s0 = COPY [[SCVTFUWSri]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s32) = G_SITOFP %0
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sitofp_s32_s64_fpr
|
||||
name: sitofp_s32_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = SCVTFUXSri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: sitofp_s32_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[SCVTFUXSri:%[0-9]+]] = SCVTFUXSri [[COPY]]
|
||||
; CHECK: %s0 = COPY [[SCVTFUXSri]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s32) = G_SITOFP %0
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sitofp_s64_s32_fpr
|
||||
name: sitofp_s64_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = SCVTFUWDri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: sitofp_s64_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SCVTFUWDri:%[0-9]+]] = SCVTFUWDri [[COPY]]
|
||||
; CHECK: %d0 = COPY [[SCVTFUWDri]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s64) = G_SITOFP %0
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sitofp_s64_s64_fpr
|
||||
name: sitofp_s64_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = SCVTFUXDri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: sitofp_s64_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[SCVTFUXDri:%[0-9]+]] = SCVTFUXDri [[COPY]]
|
||||
; CHECK: %d0 = COPY [[SCVTFUXDri]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s64) = G_SITOFP %0
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: uitofp_s32_s32_fpr
|
||||
name: uitofp_s32_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = UCVTFUWSri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: uitofp_s32_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[UCVTFUWSri:%[0-9]+]] = UCVTFUWSri [[COPY]]
|
||||
; CHECK: %s0 = COPY [[UCVTFUWSri]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s32) = G_UITOFP %0
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: uitofp_s32_s64_fpr
|
||||
name: uitofp_s32_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = UCVTFUXSri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: uitofp_s32_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[UCVTFUXSri:%[0-9]+]] = UCVTFUXSri [[COPY]]
|
||||
; CHECK: %s0 = COPY [[UCVTFUXSri]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s32) = G_UITOFP %0
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: uitofp_s64_s32_fpr
|
||||
name: uitofp_s64_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = UCVTFUWDri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: uitofp_s64_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[UCVTFUWDri:%[0-9]+]] = UCVTFUWDri [[COPY]]
|
||||
; CHECK: %d0 = COPY [[UCVTFUWDri]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s64) = G_UITOFP %0
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: uitofp_s64_s64_fpr
|
||||
name: uitofp_s64_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = UCVTFUXDri %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: uitofp_s64_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[UCVTFUXDri:%[0-9]+]] = UCVTFUXDri [[COPY]]
|
||||
; CHECK: %d0 = COPY [[UCVTFUXDri]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s64) = G_UITOFP %0
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptosi_s32_s32_gpr
|
||||
name: fptosi_s32_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %s0
|
||||
# CHECK: %1 = FCVTZSUWSr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %s0
|
||||
|
||||
; CHECK-LABEL: name: fptosi_s32_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
||||
; CHECK: [[FCVTZSUWSr:%[0-9]+]] = FCVTZSUWSr [[COPY]]
|
||||
; CHECK: %w0 = COPY [[FCVTZSUWSr]]
|
||||
%0(s32) = COPY %s0
|
||||
%1(s32) = G_FPTOSI %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptosi_s32_s64_gpr
|
||||
name: fptosi_s32_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %1 = FCVTZSUWDr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fptosi_s32_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[FCVTZSUWDr:%[0-9]+]] = FCVTZSUWDr [[COPY]]
|
||||
; CHECK: %w0 = COPY [[FCVTZSUWDr]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s32) = G_FPTOSI %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptosi_s64_s32_gpr
|
||||
name: fptosi_s64_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %s0
|
||||
# CHECK: %1 = FCVTZSUXSr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %s0
|
||||
|
||||
; CHECK-LABEL: name: fptosi_s64_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
||||
; CHECK: [[FCVTZSUXSr:%[0-9]+]] = FCVTZSUXSr [[COPY]]
|
||||
; CHECK: %x0 = COPY [[FCVTZSUXSr]]
|
||||
%0(s32) = COPY %s0
|
||||
%1(s64) = G_FPTOSI %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptosi_s64_s64_gpr
|
||||
name: fptosi_s64_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %1 = FCVTZSUXDr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fptosi_s64_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[FCVTZSUXDr:%[0-9]+]] = FCVTZSUXDr [[COPY]]
|
||||
; CHECK: %x0 = COPY [[FCVTZSUXDr]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s64) = G_FPTOSI %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptoui_s32_s32_gpr
|
||||
name: fptoui_s32_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %s0
|
||||
# CHECK: %1 = FCVTZUUWSr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %s0
|
||||
|
||||
; CHECK-LABEL: name: fptoui_s32_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
||||
; CHECK: [[FCVTZUUWSr:%[0-9]+]] = FCVTZUUWSr [[COPY]]
|
||||
; CHECK: %w0 = COPY [[FCVTZUUWSr]]
|
||||
%0(s32) = COPY %s0
|
||||
%1(s32) = G_FPTOUI %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptoui_s32_s64_gpr
|
||||
name: fptoui_s32_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %1 = FCVTZUUWDr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fptoui_s32_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[FCVTZUUWDr:%[0-9]+]] = FCVTZUUWDr [[COPY]]
|
||||
; CHECK: %w0 = COPY [[FCVTZUUWDr]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s32) = G_FPTOUI %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptoui_s64_s32_gpr
|
||||
name: fptoui_s64_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %s0
|
||||
# CHECK: %1 = FCVTZUUXSr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %s0
|
||||
|
||||
; CHECK-LABEL: name: fptoui_s64_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %s0
|
||||
; CHECK: [[FCVTZUUXSr:%[0-9]+]] = FCVTZUUXSr [[COPY]]
|
||||
; CHECK: %x0 = COPY [[FCVTZUUXSr]]
|
||||
%0(s32) = COPY %s0
|
||||
%1(s64) = G_FPTOUI %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: fptoui_s64_s64_gpr
|
||||
name: fptoui_s64_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %1 = FCVTZUUXDr %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: fptoui_s64_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[FCVTZUUXDr:%[0-9]+]] = FCVTZUUXDr [[COPY]]
|
||||
; CHECK: %x0 = COPY [[FCVTZUUXDr]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s64) = G_FPTOUI %0
|
||||
%x0 = COPY %1(s64)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -10,44 +11,44 @@
|
||||
|
||||
---
|
||||
# Check that we select a 32-bit immediate into a MOVi32imm.
|
||||
# CHECK-LABEL: name: imm_s32_gpr
|
||||
name: imm_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOVi32imm -1234
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %w1
|
||||
|
||||
; CHECK-LABEL: name: imm_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm -1234
|
||||
; CHECK: %w0 = COPY [[MOVi32imm]]
|
||||
%0(s32) = G_CONSTANT i32 -1234
|
||||
%w0 = COPY %0(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# Check that we select a 64-bit immediate into a MOVi64imm.
|
||||
# CHECK-LABEL: name: imm_s64_gpr
|
||||
name: imm_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOVi64imm 1234
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %w1
|
||||
|
||||
; CHECK-LABEL: name: imm_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234
|
||||
; CHECK: %w0 = COPY [[MOVi64imm]]
|
||||
%0(s64) = G_CONSTANT i64 1234
|
||||
%w0 = COPY %0(s64)
|
||||
...
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -7,23 +8,22 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: implicit_def
|
||||
name: implicit_def
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
# CHECK: [[ADD:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]]
|
||||
# CHECK: %w0 = COPY [[ADD]]
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: implicit_def
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]]
|
||||
; CHECK: %w0 = COPY [[ADDWrr]]
|
||||
%0(s32) = G_IMPLICIT_DEF
|
||||
%1(s32) = G_ADD %0, %0
|
||||
%w0 = COPY %1(s32)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -18,256 +19,256 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: anyext_s64_from_s32
|
||||
name: anyext_s64_from_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr64all, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %2 = SUBREG_TO_REG 0, %0, 15
|
||||
# CHECK: %1 = COPY %2
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: anyext_s64_from_s32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32all
|
||||
; CHECK-NEXT: id: 1, class: gpr64all
|
||||
; CHECK-NEXT: id: 2, class: gpr64all
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[SUBREG_TO_REG]]
|
||||
; CHECK: %x0 = COPY [[COPY1]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s64) = G_ANYEXT %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: anyext_s32_from_s8
|
||||
name: anyext_s32_from_s8
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = COPY %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: anyext_s32_from_s8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32all
|
||||
; CHECK-NEXT: id: 1, class: gpr32all
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(s8) = COPY %w0
|
||||
%1(s32) = G_ANYEXT %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: zext_s64_from_s32
|
||||
name: zext_s64_from_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %2 = SUBREG_TO_REG 0, %0, 15
|
||||
# CHECK: %1 = UBFMXri %2, 0, 31
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: zext_s64_from_s32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK-NEXT: id: 2, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15
|
||||
; CHECK: [[UBFMXri:%[0-9]+]] = UBFMXri [[SUBREG_TO_REG]], 0, 31
|
||||
; CHECK: %x0 = COPY [[UBFMXri]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s64) = G_ZEXT %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: zext_s32_from_s16
|
||||
name: zext_s32_from_s16
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = UBFMWri %0, 0, 15
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: zext_s32_from_s16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 15
|
||||
; CHECK: %w0 = COPY [[UBFMWri]]
|
||||
%0(s16) = COPY %w0
|
||||
%1(s32) = G_ZEXT %0
|
||||
%w0 = COPY %1
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: zext_s32_from_s8
|
||||
name: zext_s32_from_s8
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = UBFMWri %0, 0, 7
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: zext_s32_from_s8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 7
|
||||
; CHECK: %w0 = COPY [[UBFMWri]]
|
||||
%0(s8) = COPY %w0
|
||||
%1(s32) = G_ZEXT %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: zext_s16_from_s8
|
||||
name: zext_s16_from_s8
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = UBFMWri %0, 0, 7
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: zext_s16_from_s8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 7
|
||||
; CHECK: %w0 = COPY [[UBFMWri]]
|
||||
%0(s8) = COPY %w0
|
||||
%1(s16) = G_ZEXT %0
|
||||
%w0 = COPY %1(s16)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sext_s64_from_s32
|
||||
name: sext_s64_from_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %2 = SUBREG_TO_REG 0, %0, 15
|
||||
# CHECK: %1 = SBFMXri %2, 0, 31
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: sext_s64_from_s32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK-NEXT: id: 2, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15
|
||||
; CHECK: [[SBFMXri:%[0-9]+]] = SBFMXri [[SUBREG_TO_REG]], 0, 31
|
||||
; CHECK: %x0 = COPY [[SBFMXri]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s64) = G_SEXT %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sext_s32_from_s16
|
||||
name: sext_s32_from_s16
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = SBFMWri %0, 0, 15
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: sext_s32_from_s16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 15
|
||||
; CHECK: %w0 = COPY [[SBFMWri]]
|
||||
%0(s16) = COPY %w0
|
||||
%1(s32) = G_SEXT %0
|
||||
%w0 = COPY %1
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sext_s32_from_s8
|
||||
name: sext_s32_from_s8
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = SBFMWri %0, 0, 7
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: sext_s32_from_s8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 7
|
||||
; CHECK: %w0 = COPY [[SBFMWri]]
|
||||
%0(s8) = COPY %w0
|
||||
%1(s32) = G_SEXT %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: sext_s16_from_s8
|
||||
name: sext_s16_from_s8
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = SBFMWri %0, 0, 7
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: sext_s16_from_s8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 7
|
||||
; CHECK: %w0 = COPY [[SBFMWri]]
|
||||
%0(s8) = COPY %w0
|
||||
%1(s16) = G_SEXT %0
|
||||
%w0 = COPY %1(s16)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -12,138 +13,138 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: inttoptr_p0_s64
|
||||
name: inttoptr_p0_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
; CHECK-LABEL: name: inttoptr_p0_s64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64all
|
||||
; CHECK-NEXT: id: 1, class: gpr64all
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
|
||||
; CHECK: %x0 = COPY [[COPY1]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(p0) = G_INTTOPTR %0
|
||||
%x0 = COPY %1(p0)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: ptrtoint_s64_p0
|
||||
name: ptrtoint_s64_p0
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
; CHECK-LABEL: name: ptrtoint_s64_p0
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
|
||||
; CHECK: %x0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_PTRTOINT %0
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: ptrtoint_s32_p0
|
||||
name: ptrtoint_s32_p0
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %0.sub_32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
; CHECK-LABEL: name: ptrtoint_s32_p0
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_PTRTOINT %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: ptrtoint_s16_p0
|
||||
name: ptrtoint_s16_p0
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %0.sub_32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
; CHECK-LABEL: name: ptrtoint_s16_p0
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s16) = G_PTRTOINT %0
|
||||
%w0 = COPY %1(s16)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: ptrtoint_s8_p0
|
||||
name: ptrtoint_s8_p0
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %0.sub_32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
; CHECK-LABEL: name: ptrtoint_s8_p0
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_PTRTOINT %0
|
||||
%w0 = COPY %1(s8)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: ptrtoint_s1_p0
|
||||
name: ptrtoint_s1_p0
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %0.sub_32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
; CHECK-LABEL: name: ptrtoint_s1_p0
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s1) = G_PTRTOINT %0
|
||||
%w0 = COPY %1(s1)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -9,28 +10,28 @@
|
||||
---
|
||||
# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
|
||||
# Also check that we constrain the register class of the COPY to GPR32.
|
||||
# CHECK-LABEL: name: sdiv_s32_gpr
|
||||
name: sdiv_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: %2 = SDIVWr %0, %1
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %w1
|
||||
|
||||
; CHECK-LABEL: name: sdiv_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: [[SDIVWr:%[0-9]+]] = SDIVWr [[COPY]], [[COPY1]]
|
||||
; CHECK: %w0 = COPY [[SDIVWr]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s32) = COPY %w1
|
||||
%2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -32,114 +33,110 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s64_gpr
|
||||
name: load_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]] = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s32_gpr
|
||||
name: load_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRWui:%[0-9]+]] = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr)
|
||||
; CHECK: %w0 = COPY [[LDRWui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s16_gpr
|
||||
name: load_s16_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s16_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
|
||||
; CHECK: %w0 = COPY [[LDRHHui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
|
||||
%w0 = COPY %1(s16)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s8_gpr
|
||||
name: load_s8_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
|
||||
; CHECK: %w0 = COPY [[LDRBBui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
%w0 = COPY %1(s8)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_fi_s64_gpr
|
||||
name: load_fi_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -147,43 +144,45 @@ registers:
|
||||
stack:
|
||||
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %1 = LDRXui %stack.0.ptr0, 0 :: (load 8)
|
||||
# CHECK: %x0 = COPY %1
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_fi_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[LDRXui:%[0-9]+]] = LDRXui %stack.0.ptr0, 0 :: (load 8)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
|
||||
%1(s64) = G_LOAD %0 :: (load 8)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_128_s64_gpr
|
||||
name: load_gep_128_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRXui %0, 16 :: (load 8 from %ir.addr)
|
||||
# CHECK: %x0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_128_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]] = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 128
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -192,30 +191,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_512_s32_gpr
|
||||
name: load_gep_512_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRWui %0, 128 :: (load 4 from %ir.addr)
|
||||
# CHECK: %w0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_512_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRWui:%[0-9]+]] = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr)
|
||||
; CHECK: %w0 = COPY [[LDRWui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 512
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -224,30 +222,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_64_s16_gpr
|
||||
name: load_gep_64_s16_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRHHui %0, 32 :: (load 2 from %ir.addr)
|
||||
# CHECK: %w0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_64_s16_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
|
||||
; CHECK: %w0 = COPY [[LDRHHui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 64
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -256,30 +253,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_1_s8_gpr
|
||||
name: load_gep_1_s8_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRBBui %0, 1 :: (load 1 from %ir.addr)
|
||||
# CHECK: %w0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_1_s8_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
|
||||
; CHECK: %w0 = COPY [[LDRBBui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 1
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -288,130 +284,129 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s64_fpr
|
||||
name: load_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
|
||||
; CHECK: %d0 = COPY [[LDRDui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
|
||||
%d0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s32_fpr
|
||||
name: load_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRSui:%[0-9]+]] = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr)
|
||||
; CHECK: %s0 = COPY [[LDRSui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
|
||||
%s0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s16_fpr
|
||||
name: load_s16_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s16_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr16
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRHui:%[0-9]+]] = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr)
|
||||
; CHECK: %h0 = COPY [[LDRHui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
|
||||
%h0 = COPY %1(s16)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_s8_fpr
|
||||
name: load_s8_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr8
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRBui:%[0-9]+]] = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr)
|
||||
; CHECK: %b0 = COPY [[LDRBui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
%b0 = COPY %1(s8)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_8_s64_fpr
|
||||
name: load_gep_8_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRDui %0, 1 :: (load 8 from %ir.addr)
|
||||
# CHECK: %d0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_8_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr)
|
||||
; CHECK: %d0 = COPY [[LDRDui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 8
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -420,30 +415,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_16_s32_fpr
|
||||
name: load_gep_16_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRSui %0, 4 :: (load 4 from %ir.addr)
|
||||
# CHECK: %s0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_16_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRSui:%[0-9]+]] = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr)
|
||||
; CHECK: %s0 = COPY [[LDRSui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 16
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -452,30 +446,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_64_s16_fpr
|
||||
name: load_gep_64_s16_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: fpr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRHui %0, 32 :: (load 2 from %ir.addr)
|
||||
# CHECK: %h0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_64_s16_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: fpr16
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRHui:%[0-9]+]] = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr)
|
||||
; CHECK: %h0 = COPY [[LDRHui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 64
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -484,30 +477,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: load_gep_32_s8_fpr
|
||||
name: load_gep_32_s8_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: fpr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %3 = LDRBui %0, 32 :: (load 1 from %ir.addr)
|
||||
# CHECK: %b0 = COPY %3
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_gep_32_s8_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: fpr8
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRBui:%[0-9]+]] = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr)
|
||||
; CHECK: %b0 = COPY [[LDRBui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 32
|
||||
%2(p0) = G_GEP %0, %1
|
||||
@ -515,26 +507,25 @@ body: |
|
||||
%b0 = COPY %3
|
||||
...
|
||||
---
|
||||
# CHECK-LABEL: name: load_v2s32
|
||||
name: load_v2s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr)
|
||||
# CHECK: %d0 = COPY %1
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_v2s32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
|
||||
; CHECK: %d0 = COPY [[LDRDui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr)
|
||||
%d0 = COPY %1(<2 x s32>)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -7,19 +8,10 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: SMADDLrrr_gpr
|
||||
name: SMADDLrrr_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 6, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -29,15 +21,24 @@ registers:
|
||||
- { id: 5, class: gpr }
|
||||
- { id: 6, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: %2 = COPY %w2
|
||||
# CHECK: %6 = SMADDLrrr %1, %2, %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1, %w2
|
||||
|
||||
; CHECK-LABEL: name: SMADDLrrr_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr32
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK-NEXT: id: 4, class: gpr
|
||||
; CHECK-NEXT: id: 5, class: gpr
|
||||
; CHECK-NEXT: id: 6, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: [[COPY2:%[0-9]+]] = COPY %w2
|
||||
; CHECK: [[SMADDLrrr:%[0-9]+]] = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
|
||||
; CHECK: %x0 = COPY [[SMADDLrrr]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s32) = COPY %w1
|
||||
%2(s32) = COPY %w2
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -8,28 +9,27 @@
|
||||
|
||||
---
|
||||
# Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
|
||||
# CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
|
||||
name: vcvtfxu2fp_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %d0
|
||||
# CHECK: %2 = UCVTFd %0, 12
|
||||
# CHECK: %d1 = COPY %2
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %d0
|
||||
|
||||
; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: fpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %d0
|
||||
; CHECK: [[UCVTFd:%[0-9]+]] = UCVTFd [[COPY]], 12
|
||||
; CHECK: %d1 = COPY [[UCVTFd]]
|
||||
%0(s64) = COPY %d0
|
||||
%1(s32) = G_CONSTANT i32 12
|
||||
%2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -29,26 +30,25 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_s64_gpr
|
||||
name: store_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %x1
|
||||
# CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %x1
|
||||
|
||||
; CHECK-LABEL: name: store_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
|
||||
; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = COPY %x1
|
||||
G_STORE %1, %0 :: (store 8 into %ir.addr)
|
||||
@ -56,26 +56,25 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_s32_gpr
|
||||
name: store_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1
|
||||
|
||||
; CHECK-LABEL: name: store_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = COPY %w1
|
||||
G_STORE %1, %0 :: (store 4 into %ir.addr)
|
||||
@ -83,26 +82,25 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_s16_gpr
|
||||
name: store_s16_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1
|
||||
|
||||
; CHECK-LABEL: name: store_s16_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s16) = COPY %w1
|
||||
G_STORE %1, %0 :: (store 2 into %ir.addr)
|
||||
@ -110,26 +108,25 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_s8_gpr
|
||||
name: store_s8_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1
|
||||
|
||||
; CHECK-LABEL: name: store_s8_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = COPY %w1
|
||||
G_STORE %1, %0 :: (store 1 into %ir.addr)
|
||||
@ -137,25 +134,24 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_zero_s64_gpr
|
||||
name: store_zero_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: STRXui %xzr, %0, 0 :: (store 8 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %x1
|
||||
|
||||
; CHECK-LABEL: name: store_zero_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: STRXui %xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 0
|
||||
G_STORE %1, %0 :: (store 8 into %ir.addr)
|
||||
@ -163,25 +159,24 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_zero_s32_gpr
|
||||
name: store_zero_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: STRWui %wzr, %0, 0 :: (store 4 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: store_zero_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: STRWui %wzr, [[COPY]], 0 :: (store 4 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_CONSTANT i32 0
|
||||
G_STORE %1, %0 :: (store 4 into %ir.addr)
|
||||
@ -189,14 +184,10 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_fi_s64_gpr
|
||||
name: store_fi_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -204,43 +195,45 @@ registers:
|
||||
stack:
|
||||
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: STRXui %0, %stack.0.ptr0, 0 :: (store 8)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: store_fi_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
|
||||
%0(p0) = COPY %x0
|
||||
%1(p0) = G_FRAME_INDEX %stack.0.ptr0
|
||||
G_STORE %0, %1 :: (store 8)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_gep_128_s64_gpr
|
||||
name: store_gep_128_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %x1
|
||||
# CHECK: STRXui %1, %0, 16 :: (store 8 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %x1
|
||||
|
||||
; CHECK-LABEL: name: store_gep_128_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
|
||||
; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store 8 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = COPY %x1
|
||||
%2(s64) = G_CONSTANT i64 128
|
||||
@ -249,30 +242,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_gep_512_s32_gpr
|
||||
name: store_gep_512_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: STRWui %1, %0, 128 :: (store 4 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1
|
||||
|
||||
; CHECK-LABEL: name: store_gep_512_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store 4 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = COPY %w1
|
||||
%2(s64) = G_CONSTANT i64 512
|
||||
@ -281,30 +273,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_gep_64_s16_gpr
|
||||
name: store_gep_64_s16_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: STRHHui %1, %0, 32 :: (store 2 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1
|
||||
|
||||
; CHECK-LABEL: name: store_gep_64_s16_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s16) = COPY %w1
|
||||
%2(s64) = G_CONSTANT i64 64
|
||||
@ -313,30 +304,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_gep_1_s8_gpr
|
||||
name: store_gep_1_s8_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: STRBBui %1, %0, 1 :: (store 1 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %w1
|
||||
|
||||
; CHECK-LABEL: name: store_gep_1_s8_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = COPY %w1
|
||||
%2(s64) = G_CONSTANT i64 1
|
||||
@ -345,26 +335,25 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_s64_fpr
|
||||
name: store_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %d1
|
||||
# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %d1
|
||||
|
||||
; CHECK-LABEL: name: store_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
|
||||
; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = COPY %d1
|
||||
G_STORE %1, %0 :: (store 8 into %ir.addr)
|
||||
@ -372,26 +361,25 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_s32_fpr
|
||||
name: store_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %s1
|
||||
# CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %s1
|
||||
|
||||
; CHECK-LABEL: name: store_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
|
||||
; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = COPY %s1
|
||||
G_STORE %1, %0 :: (store 4 into %ir.addr)
|
||||
@ -399,30 +387,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_gep_8_s64_fpr
|
||||
name: store_gep_8_s64_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %d1
|
||||
# CHECK: STRDui %1, %0, 1 :: (store 8 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %d1
|
||||
|
||||
; CHECK-LABEL: name: store_gep_8_s64_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr64
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
|
||||
; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store 8 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = COPY %d1
|
||||
%2(s64) = G_CONSTANT i64 8
|
||||
@ -431,30 +418,29 @@ body: |
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: store_gep_8_s32_fpr
|
||||
name: store_gep_8_s32_fpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %s1
|
||||
# CHECK: STRSui %1, %0, 2 :: (store 4 into %ir.addr)
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %s1
|
||||
|
||||
; CHECK-LABEL: name: store_gep_8_s32_fpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: fpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gpr
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
|
||||
; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store 4 into %ir.addr)
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = COPY %s1
|
||||
%2(s64) = G_CONSTANT i64 8
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -9,72 +10,75 @@
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: trunc_s32_s64
|
||||
name: trunc_s32_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32sp, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %1 = COPY %0.sub_32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: trunc_s32_s64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64sp
|
||||
; CHECK-NEXT: id: 1, class: gpr32sp
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s32) = G_TRUNC %0
|
||||
%w0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: trunc_s8_s64
|
||||
name: trunc_s8_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %1 = COPY %0.sub_32
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: trunc_s8_s64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s8) = G_TRUNC %0
|
||||
%w0 = COPY %1(s8)
|
||||
...
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: trunc_s1_s32
|
||||
name: trunc_s1_s32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %1 = COPY %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: trunc_s1_s32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
|
||||
; CHECK: %w0 = COPY [[COPY1]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s1) = G_TRUNC %0
|
||||
%w0 = COPY %1(s1)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -14,28 +15,28 @@
|
||||
---
|
||||
# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
|
||||
# Also check that we constrain the register class of the COPY to GPR32.
|
||||
# CHECK-LABEL: name: xor_s32_gpr
|
||||
name: xor_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %1 = COPY %w1
|
||||
# CHECK: %2 = EORWrr %0, %1
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0, %w1
|
||||
|
||||
; CHECK-LABEL: name: xor_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr32
|
||||
; CHECK-NEXT: id: 2, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
|
||||
; CHECK: [[EORWrr:%[0-9]+]] = EORWrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %w0 = COPY [[EORWrr]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s32) = COPY %w1
|
||||
%2(s32) = G_XOR %0, %1
|
||||
@ -44,28 +45,28 @@ body: |
|
||||
|
||||
---
|
||||
# Same as xor_s64_gpr, for 64-bit operations.
|
||||
# CHECK-LABEL: name: xor_s64_gpr
|
||||
name: xor_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %1 = COPY %x1
|
||||
# CHECK: %2 = EORXrr %0, %1
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0, %x1
|
||||
|
||||
; CHECK-LABEL: name: xor_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr64
|
||||
; CHECK-NEXT: id: 2, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
|
||||
; CHECK: [[EORXrr:%[0-9]+]] = EORXrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %x0 = COPY [[EORXrr]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s64) = COPY %x1
|
||||
%2(s64) = G_XOR %0, %1
|
||||
@ -75,27 +76,27 @@ body: |
|
||||
---
|
||||
# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32.
|
||||
# Also check that we constrain the register class of the COPY to GPR32.
|
||||
# CHECK-LABEL: name: xor_constant_n1_s32_gpr
|
||||
name: xor_constant_n1_s32_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %2 = ORNWrr %wzr, %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %w0
|
||||
|
||||
; CHECK-LABEL: name: xor_constant_n1_s32_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[ORNWrr:%[0-9]+]] = ORNWrr %wzr, [[COPY]]
|
||||
; CHECK: %w0 = COPY [[ORNWrr]]
|
||||
%0(s32) = COPY %w0
|
||||
%1(s32) = G_CONSTANT i32 -1
|
||||
%2(s32) = G_XOR %0, %1
|
||||
@ -104,27 +105,27 @@ body: |
|
||||
|
||||
---
|
||||
# Same as xor_constant_n1_s64_gpr, for 64-bit operations.
|
||||
# CHECK-LABEL: name: xor_constant_n1_s64_gpr
|
||||
name: xor_constant_n1_s64_gpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = COPY %x0
|
||||
# CHECK: %2 = ORNXrr %xzr, %0
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: xor_constant_n1_s64_gpr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr64
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %x0
|
||||
; CHECK: [[ORNXrr:%[0-9]+]] = ORNXrr %xzr, [[COPY]]
|
||||
; CHECK: %x0 = COPY [[ORNXrr]]
|
||||
%0(s64) = COPY %x0
|
||||
%1(s64) = G_CONSTANT i64 -1
|
||||
%2(s64) = G_XOR %0, %1
|
||||
@ -133,26 +134,29 @@ body: |
|
||||
|
||||
---
|
||||
# Check that we can obtain constants from other basic blocks.
|
||||
# CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
|
||||
name: xor_constant_n1_s32_gpr_2bb
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: B %bb.1
|
||||
# CHECK: %0 = COPY %w0
|
||||
# CHECK: %2 = ORNWrr %wzr, %0
|
||||
|
||||
body: |
|
||||
; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gpr32
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr32
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: B %bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %w0
|
||||
; CHECK: [[ORNWrr:%[0-9]+]] = ORNWrr %wzr, [[COPY]]
|
||||
; CHECK: %w0 = COPY [[ORNWrr]]
|
||||
bb.0:
|
||||
liveins: %w0, %w1
|
||||
successors: %bb.1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -26,23 +27,27 @@
|
||||
...
|
||||
---
|
||||
name: test_add_v64i8
|
||||
# ALL-LABEL: name: test_add_v64i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPADDBZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_add_v64i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPADDBZrr:%[0-9]+]] = VPADDBZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPADDBZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<64 x s8>) = COPY %zmm0
|
||||
%1(<64 x s8>) = COPY %zmm1
|
||||
%2(<64 x s8>) = G_ADD %0, %1
|
||||
@ -52,23 +57,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_add_v32i16
|
||||
# ALL-LABEL: name: test_add_v32i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPADDWZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_add_v32i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPADDWZrr:%[0-9]+]] = VPADDWZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPADDWZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<32 x s16>) = COPY %zmm0
|
||||
%1(<32 x s16>) = COPY %zmm1
|
||||
%2(<32 x s16>) = G_ADD %0, %1
|
||||
@ -78,23 +87,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_add_v16i32
|
||||
# ALL-LABEL: name: test_add_v16i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPADDDZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_add_v16i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPADDDZrr:%[0-9]+]] = VPADDDZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPADDDZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<16 x s32>) = COPY %zmm1
|
||||
%2(<16 x s32>) = G_ADD %0, %1
|
||||
@ -104,23 +117,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_add_v8i64
|
||||
# ALL-LABEL: name: test_add_v8i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPADDQZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_add_v8i64
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPADDQZrr:%[0-9]+]] = VPADDQZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPADDQZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<8 x s64>) = COPY %zmm0
|
||||
%1(<8 x s64>) = COPY %zmm1
|
||||
%2(<8 x s64>) = G_ADD %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X32
|
||||
--- |
|
||||
define i64 @test_add_i64(i64 %a, i64 %b) {
|
||||
@ -8,21 +9,9 @@
|
||||
...
|
||||
---
|
||||
name: test_add_i64
|
||||
# X32-LABEL: name: test_add_i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# X32: registers:
|
||||
# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 4, class: gpr, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 5, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 6, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 7, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 8, class: gr32, preferred-register: '' }
|
||||
# X32-NEXT: - { id: 9, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -34,20 +23,32 @@ registers:
|
||||
- { id: 7, class: gpr }
|
||||
- { id: 8, class: gpr }
|
||||
- { id: 9, class: gpr }
|
||||
# X32: %0 = IMPLICIT_DEF
|
||||
# X32-NEXT: %1 = IMPLICIT_DEF
|
||||
# X32-NEXT: %2 = IMPLICIT_DEF
|
||||
# X32-NEXT: %3 = IMPLICIT_DEF
|
||||
# X32-NEXT: %5 = ADD32rr %0, %2, implicit-def %eflags
|
||||
# X32-NEXT: %6 = COPY %eflags
|
||||
# X32-NEXT: %eflags = COPY %6
|
||||
# X32-NEXT: %7 = ADC32rr %1, %3, implicit-def %eflags, implicit %eflags
|
||||
# X32-NEXT: %8 = COPY %eflags
|
||||
# X32-NEXT: %eax = COPY %5
|
||||
# X32-NEXT: %edx = COPY %7
|
||||
# X32-NEXT: RET 0, implicit %eax, implicit %edx
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
; X32-LABEL: name: test_add_i64
|
||||
; X32: registers:
|
||||
; X32-NEXT: id: 0, class: gr32
|
||||
; X32-NEXT: id: 1, class: gr32
|
||||
; X32-NEXT: id: 2, class: gr32
|
||||
; X32-NEXT: id: 3, class: gr32
|
||||
; X32-NEXT: id: 4, class: gpr
|
||||
; X32-NEXT: id: 5, class: gr32
|
||||
; X32-NEXT: id: 6, class: gr32
|
||||
; X32-NEXT: id: 7, class: gr32
|
||||
; X32-NEXT: id: 8, class: gr32
|
||||
; X32-NEXT: id: 9, class: gpr
|
||||
; X32: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; X32: [[DEF1:%[0-9]+]] = IMPLICIT_DEF
|
||||
; X32: [[DEF2:%[0-9]+]] = IMPLICIT_DEF
|
||||
; X32: [[DEF3:%[0-9]+]] = IMPLICIT_DEF
|
||||
; X32: [[ADD32rr:%[0-9]+]] = ADD32rr [[DEF]], [[DEF2]], implicit-def %eflags
|
||||
; X32: [[COPY:%[0-9]+]] = COPY %eflags
|
||||
; X32: %eflags = COPY [[COPY]]
|
||||
; X32: [[ADC32rr:%[0-9]+]] = ADC32rr [[DEF1]], [[DEF3]], implicit-def %eflags, implicit %eflags
|
||||
; X32: [[COPY1:%[0-9]+]] = COPY %eflags
|
||||
; X32: %eax = COPY [[ADD32rr]]
|
||||
; X32: %edx = COPY [[ADC32rr]]
|
||||
; X32: RET 0, implicit %eax, implicit %edx
|
||||
%0(s32) = IMPLICIT_DEF
|
||||
%1(s32) = IMPLICIT_DEF
|
||||
%2(s32) = IMPLICIT_DEF
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -24,14 +25,9 @@
|
||||
...
|
||||
---
|
||||
name: test_and_i8
|
||||
# ALL-LABEL: name: test_and_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -40,15 +36,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %dil
|
||||
# ALL-NEXT: %1 = COPY %sil
|
||||
# ALL-NEXT: %2 = AND8rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %al = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_and_i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr8
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %sil
|
||||
; ALL: [[AND8rr:%[0-9]+]] = AND8rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %al = COPY [[AND8rr]]
|
||||
; ALL: RET 0, implicit %al
|
||||
%0(s8) = COPY %dil
|
||||
%1(s8) = COPY %sil
|
||||
%2(s8) = G_AND %0, %1
|
||||
@ -58,14 +59,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_and_i16
|
||||
# ALL-LABEL: name: test_and_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -74,15 +70,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %di
|
||||
# ALL-NEXT: %1 = COPY %si
|
||||
# ALL-NEXT: %2 = AND16rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %ax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_and_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr16
|
||||
; ALL-NEXT: id: 1, class: gr16
|
||||
; ALL-NEXT: id: 2, class: gr16
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %di
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %si
|
||||
; ALL: [[AND16rr:%[0-9]+]] = AND16rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %ax = COPY [[AND16rr]]
|
||||
; ALL: RET 0, implicit %ax
|
||||
%0(s16) = COPY %di
|
||||
%1(s16) = COPY %si
|
||||
%2(s16) = G_AND %0, %1
|
||||
@ -92,14 +93,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_and_i32
|
||||
# ALL-LABEL: name: test_and_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -108,15 +104,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %edi
|
||||
# ALL-NEXT: %1 = COPY %esi
|
||||
# ALL-NEXT: %2 = AND32rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %eax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_and_i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gr32
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; ALL: [[AND32rr:%[0-9]+]] = AND32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %eax = COPY [[AND32rr]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s32) = G_AND %0, %1
|
||||
@ -126,14 +127,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_and_i64
|
||||
# ALL-LABEL: name: test_and_i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -142,15 +138,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %rsi
|
||||
# ALL-NEXT: %2 = AND64rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %rsi
|
||||
|
||||
; ALL-LABEL: name: test_and_i64
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64
|
||||
; ALL-NEXT: id: 1, class: gr64
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
|
||||
; ALL: [[AND64rr:%[0-9]+]] = AND64rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %rax = COPY [[AND64rr]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s64) = COPY %rsi
|
||||
%2(s64) = G_AND %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||||
#
|
||||
# Test that rules where multiple operands must be the same operand successfully
|
||||
@ -9,26 +10,28 @@
|
||||
|
||||
---
|
||||
name: test_blsi32rr
|
||||
# CHECK-LABEL: name: test_blsi32rr
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# G_SUB and G_AND both use %0 so we should match this.
|
||||
# CHECK: %3 = BLSI32rr %0
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: test_blsi32rr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[BLSI32rr:%[0-9]+]] = BLSI32rr [[COPY]], implicit-def %eflags
|
||||
; CHECK: %edi = COPY [[BLSI32rr]]
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = G_CONSTANT i32 0
|
||||
%2(s32) = G_SUB %1, %0
|
||||
@ -38,7 +41,6 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_blsi32rr_nomatch
|
||||
# CHECK-LABEL: name: test_blsi32rr_nomatch
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -48,11 +50,21 @@ registers:
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# G_SUB and G_AND use different operands so we shouldn't match this.
|
||||
# CHECK-NOT: BLSI32rr
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: test_blsi32rr_nomatch
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr32
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[MOV32r0_:%[0-9]+]] = MOV32r0 implicit-def %eflags
|
||||
; CHECK: [[SUB32ri:%[0-9]+]] = SUB32ri [[MOV32r0_]], 0, implicit-def %eflags
|
||||
; CHECK: [[AND32rr:%[0-9]+]] = AND32rr [[SUB32ri]], [[COPY]], implicit-def %eflags
|
||||
; CHECK: %edi = COPY [[AND32rr]]
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = G_CONSTANT i32 0
|
||||
%2(s32) = G_SUB %1, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||||
#
|
||||
# Test that rules where multiple operands must be the same operand successfully
|
||||
@ -6,26 +7,28 @@
|
||||
|
||||
---
|
||||
name: test_blsr32rr
|
||||
# CHECK-LABEL: name: test_blsr32rr
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# G_ADD and G_AND both use %0 so we should match this.
|
||||
# CHECK: %3 = BLSR32rr %0
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: test_blsr32rr
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gpr
|
||||
; CHECK-NEXT: id: 2, class: gpr
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[BLSR32rr:%[0-9]+]] = BLSR32rr [[COPY]], implicit-def %eflags
|
||||
; CHECK: %edi = COPY [[BLSR32rr]]
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = G_CONSTANT i32 -1
|
||||
%2(s32) = G_ADD %0, %1
|
||||
@ -35,7 +38,6 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_blsr32rr_nomatch
|
||||
# CHECK-LABEL: name: test_blsr32rr_nomatch
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
@ -45,11 +47,21 @@ registers:
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# G_ADD and G_AND use different operands so we shouldn't match this.
|
||||
# CHECK-NOT: BLSR32rr
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: test_blsr32rr_nomatch
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr32
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 4294967295
|
||||
; CHECK: [[DEC32r:%[0-9]+]] = DEC32r [[MOV32ri]], implicit-def %eflags
|
||||
; CHECK: [[AND32rr:%[0-9]+]] = AND32rr [[DEC32r]], [[COPY]], implicit-def %eflags
|
||||
; CHECK: %edi = COPY [[AND32rr]]
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = G_CONSTANT i32 -1
|
||||
%2(s32) = G_ADD %1, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
--- |
|
||||
@ -82,33 +83,33 @@
|
||||
...
|
||||
---
|
||||
name: test_icmp_eq_i8
|
||||
# CHECK-LABEL: name: test_icmp_eq_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %dil
|
||||
# CHECK-NEXT: %1 = COPY %sil
|
||||
# CHECK-NEXT: CMP8rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_eq_i8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr8
|
||||
; CHECK-NEXT: id: 1, class: gr8
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %sil
|
||||
; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s8) = COPY %dil
|
||||
%1(s8) = COPY %sil
|
||||
%2(s1) = G_ICMP intpred(eq), %0(s8), %1
|
||||
@ -119,33 +120,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_eq_i16
|
||||
# CHECK-LABEL: name: test_icmp_eq_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %di
|
||||
# CHECK-NEXT: %1 = COPY %si
|
||||
# CHECK-NEXT: CMP16rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_eq_i16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr16
|
||||
; CHECK-NEXT: id: 1, class: gr16
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %di
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %si
|
||||
; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s16) = COPY %di
|
||||
%1(s16) = COPY %si
|
||||
%2(s1) = G_ICMP intpred(eq), %0(s16), %1
|
||||
@ -156,33 +157,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_eq_i64
|
||||
# CHECK-LABEL: name: test_icmp_eq_i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %rdi
|
||||
# CHECK-NEXT: %1 = COPY %rsi
|
||||
# CHECK-NEXT: CMP64rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %rsi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_eq_i64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK-NEXT: id: 1, class: gr64
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %rsi
|
||||
; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s64) = COPY %rsi
|
||||
%2(s1) = G_ICMP intpred(eq), %0(s64), %1
|
||||
@ -193,33 +194,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_eq_i32
|
||||
# CHECK-LABEL: name: test_icmp_eq_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_eq_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
|
||||
@ -230,33 +231,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_ne_i32
|
||||
# CHECK-LABEL: name: test_icmp_ne_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETNEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_ne_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETNEr:%[0-9]+]] = SETNEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETNEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(ne), %0(s32), %1
|
||||
@ -267,33 +268,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_ugt_i32
|
||||
# CHECK-LABEL: name: test_icmp_ugt_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETAr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_ugt_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETAr:%[0-9]+]] = SETAr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETAr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
|
||||
@ -304,33 +305,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_uge_i32
|
||||
# CHECK-LABEL: name: test_icmp_uge_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETAEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_uge_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETAEr:%[0-9]+]] = SETAEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETAEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(uge), %0(s32), %1
|
||||
@ -341,33 +342,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_ult_i32
|
||||
# CHECK-LABEL: name: test_icmp_ult_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETBr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_ult_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETBr:%[0-9]+]] = SETBr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETBr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
|
||||
@ -378,33 +379,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_ule_i32
|
||||
# CHECK-LABEL: name: test_icmp_ule_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETBEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_ule_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETBEr:%[0-9]+]] = SETBEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETBEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(ule), %0(s32), %1
|
||||
@ -415,33 +416,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_sgt_i32
|
||||
# CHECK-LABEL: name: test_icmp_sgt_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETGr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_sgt_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETGr:%[0-9]+]] = SETGr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETGr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
|
||||
@ -452,33 +453,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_sge_i32
|
||||
# CHECK-LABEL: name: test_icmp_sge_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETGEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_sge_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETGEr:%[0-9]+]] = SETGEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETGEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
|
||||
@ -489,33 +490,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_slt_i32
|
||||
# CHECK-LABEL: name: test_icmp_slt_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETLr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_slt_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETLr:%[0-9]+]] = SETLr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETLr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
|
||||
@ -526,33 +527,33 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_icmp_sle_i32
|
||||
# CHECK-LABEL: name: test_icmp_sle_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
- { id: 3, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %esi
|
||||
# CHECK-NEXT: CMP32rr %0, %1, implicit-def %eflags
|
||||
# CHECK-NEXT: %2 = SETLEr implicit %eflags
|
||||
# CHECK-NEXT: %4 = SUBREG_TO_REG 0, %2, 1
|
||||
# CHECK-NEXT: %3 = AND32ri8 %4, 1, implicit-def %eflags
|
||||
# CHECK-NEXT: %eax = COPY %3
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; CHECK-LABEL: name: test_icmp_sle_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK-NEXT: id: 2, class: gr8
|
||||
; CHECK-NEXT: id: 3, class: gr32
|
||||
; CHECK-NEXT: id: 4, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; CHECK: [[SETLEr:%[0-9]+]] = SETLEr implicit %eflags
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETLEr]], 1
|
||||
; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[AND32ri8_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
--- |
|
||||
@ -40,15 +41,16 @@ name: const_i8
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i8
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV8ri 2
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr8
|
||||
; CHECK: [[MOV8ri:%[0-9]+]] = MOV8ri 2
|
||||
; CHECK: %al = COPY [[MOV8ri]]
|
||||
; CHECK: RET 0, implicit %al
|
||||
%0(s8) = G_CONSTANT i8 2
|
||||
%al = COPY %0(s8)
|
||||
RET 0, implicit %al
|
||||
@ -59,15 +61,16 @@ name: const_i16
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i16
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV16ri 3
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr16
|
||||
; CHECK: [[MOV16ri:%[0-9]+]] = MOV16ri 3
|
||||
; CHECK: %ax = COPY [[MOV16ri]]
|
||||
; CHECK: RET 0, implicit %ax
|
||||
%0(s16) = G_CONSTANT i16 3
|
||||
%ax = COPY %0(s16)
|
||||
RET 0, implicit %ax
|
||||
@ -78,15 +81,16 @@ name: const_i32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i32
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV32ri 4
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 4
|
||||
; CHECK: %eax = COPY [[MOV32ri]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = G_CONSTANT i32 4
|
||||
%eax = COPY %0(s32)
|
||||
RET 0, implicit %eax
|
||||
@ -94,16 +98,18 @@ body: |
|
||||
...
|
||||
---
|
||||
name: const_i32_0
|
||||
# CHECK-LABEL: name: const_i32_0
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: %0 = MOV32r0 implicit-def %eflags
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i32_0
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK: [[MOV32r0_:%[0-9]+]] = MOV32r0 implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[MOV32r0_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = G_CONSTANT i32 0
|
||||
%eax = COPY %0(s32)
|
||||
RET 0, implicit %eax
|
||||
@ -114,15 +120,16 @@ name: const_i64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i64
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV64ri 68719476720
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK: [[MOV64ri:%[0-9]+]] = MOV64ri 68719476720
|
||||
; CHECK: %rax = COPY [[MOV64ri]]
|
||||
; CHECK: RET 0, implicit %rax
|
||||
%0(s64) = G_CONSTANT i64 68719476720
|
||||
%rax = COPY %0(s64)
|
||||
RET 0, implicit %rax
|
||||
@ -134,15 +141,16 @@ alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i64_u32
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV64ri32 1879048192
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i64_u32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 1879048192
|
||||
; CHECK: %rax = COPY [[MOV64ri32_]]
|
||||
; CHECK: RET 0, implicit %rax
|
||||
%0(s64) = G_CONSTANT i64 1879048192
|
||||
%rax = COPY %0(s64)
|
||||
RET 0, implicit %rax
|
||||
@ -153,15 +161,16 @@ name: const_i64_i32
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i64_i32
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV64ri32 -1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i64_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 -1
|
||||
; CHECK: %rax = COPY [[MOV64ri32_]]
|
||||
; CHECK: RET 0, implicit %rax
|
||||
%0(s64) = G_CONSTANT i64 -1
|
||||
%rax = COPY %0(s64)
|
||||
RET 0, implicit %rax
|
||||
@ -169,24 +178,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: main
|
||||
# CHECK-LABEL: name: main
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
# CHECK: %0 = COPY %rdi
|
||||
# CHECK-NEXT: %1 = MOV64ri32 0
|
||||
# CHECK-NEXT: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.data)
|
||||
# CHECK-NEXT: RET 0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; CHECK-LABEL: name: main
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK-NEXT: id: 1, class: gr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 0
|
||||
; CHECK: MOV64mr [[COPY]], 1, _, 0, _, [[MOV64ri32_]] :: (store 8 into %ir.data)
|
||||
; CHECK: RET 0
|
||||
%0(p0) = COPY %rdi
|
||||
%1(p0) = G_CONSTANT i64 0
|
||||
G_STORE %1(p0), %0(p0) :: (store 8 into %ir.data)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
|
||||
|
||||
--- |
|
||||
@ -24,29 +25,29 @@
|
||||
...
|
||||
---
|
||||
name: test_zext_i1
|
||||
# ALL-LABEL: name: test_zext_i1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: %0 = COPY %dil
|
||||
# ALL-NEXT: %1 = COPY %0
|
||||
# ALL-NEXT: %3 = SUBREG_TO_REG 0, %1, 1
|
||||
# ALL-NEXT: %2 = AND64ri8 %3, 1, implicit-def %eflags
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: test_zext_i1
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL-NEXT: id: 3, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]]
|
||||
; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
|
||||
; ALL: [[AND64ri8_:%[0-9]+]] = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
|
||||
; ALL: %rax = COPY [[AND64ri8_]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s8) = COPY %dil
|
||||
%1(s1) = G_TRUNC %0(s8)
|
||||
%2(s64) = G_ZEXT %1(s1)
|
||||
@ -56,24 +57,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_sext_i8
|
||||
# ALL-LABEL: name: test_sext_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# ALL: %0 = COPY %dil
|
||||
# ALL-NEXT: %1 = MOVSX64rr8 %0
|
||||
# ALL-NEXT: %rax = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: test_sext_i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; ALL: [[MOVSX64rr8_:%[0-9]+]] = MOVSX64rr8 [[COPY]]
|
||||
; ALL: %rax = COPY [[MOVSX64rr8_]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s8) = COPY %dil
|
||||
%1(s64) = G_SEXT %0(s8)
|
||||
%rax = COPY %1(s64)
|
||||
@ -82,24 +83,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_sext_i16
|
||||
# ALL-LABEL: name: test_sext_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# ALL: %0 = COPY %di
|
||||
# ALL-NEXT: %1 = MOVSX64rr16 %0
|
||||
# ALL-NEXT: %rax = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: test_sext_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr16
|
||||
; ALL-NEXT: id: 1, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %di
|
||||
; ALL: [[MOVSX64rr16_:%[0-9]+]] = MOVSX64rr16 [[COPY]]
|
||||
; ALL: %rax = COPY [[MOVSX64rr16_]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s16) = COPY %di
|
||||
%1(s64) = G_SEXT %0(s16)
|
||||
%rax = COPY %1(s64)
|
||||
@ -108,27 +109,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: anyext_s64_from_s1
|
||||
# ALL-LABEL: name: anyext_s64_from_s1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %0.sub_8bit
|
||||
# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 1
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: anyext_s64_from_s1
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64_with_sub_8bit
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
|
||||
; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
|
||||
; ALL: %rax = COPY [[SUBREG_TO_REG]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s1) = G_TRUNC %0(s64)
|
||||
%2(s64) = G_ANYEXT %1(s1)
|
||||
@ -137,27 +138,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: anyext_s64_from_s8
|
||||
# ALL-LABEL: name: anyext_s64_from_s8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %0.sub_8bit
|
||||
# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 1
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: anyext_s64_from_s8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64_with_sub_8bit
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
|
||||
; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
|
||||
; ALL: %rax = COPY [[SUBREG_TO_REG]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s8) = G_TRUNC %0(s64)
|
||||
%2(s64) = G_ANYEXT %1(s8)
|
||||
@ -166,27 +167,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: anyext_s64_from_s16
|
||||
# ALL-LABEL: name: anyext_s64_from_s16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %0.sub_16bit
|
||||
# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 3
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: anyext_s64_from_s16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64
|
||||
; ALL-NEXT: id: 1, class: gr16
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
|
||||
; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 3
|
||||
; ALL: %rax = COPY [[SUBREG_TO_REG]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s16) = G_TRUNC %0(s64)
|
||||
%2(s64) = G_ANYEXT %1(s16)
|
||||
@ -195,27 +196,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: anyext_s64_from_s32
|
||||
# ALL-LABEL: name: anyext_s64_from_s32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %0.sub_32bit
|
||||
# ALL-NEXT: %2 = SUBREG_TO_REG 0, %1, 4
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: anyext_s64_from_s32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32bit
|
||||
; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 4
|
||||
; ALL: %rax = COPY [[SUBREG_TO_REG]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s32) = G_TRUNC %0(s64)
|
||||
%2(s64) = G_ANYEXT %1(s32)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
--- |
|
||||
|
||||
@ -10,13 +11,9 @@
|
||||
...
|
||||
---
|
||||
name: test
|
||||
# ALL-LABEL: name: test
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: fr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: fr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr, preferred-register: '' }
|
||||
- { id: 1, class: vecr, preferred-register: '' }
|
||||
@ -24,14 +21,18 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %xmm0
|
||||
# ALL-NEXT: %1 = CVTSS2SDrr %0
|
||||
# ALL-NEXT: %xmm0 = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %xmm0
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: %xmm0
|
||||
|
||||
; ALL-LABEL: name: test
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: fr32
|
||||
; ALL-NEXT: id: 1, class: fr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; ALL: [[CVTSS2SDrr:%[0-9]+]] = CVTSS2SDrr [[COPY]]
|
||||
; ALL: %xmm0 = COPY [[CVTSS2SDrr]]
|
||||
; ALL: RET 0, implicit %xmm0
|
||||
%0(s32) = COPY %xmm0
|
||||
%1(s64) = G_FPEXT %0(s32)
|
||||
%xmm0 = COPY %1(s64)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
--- |
|
||||
@ -12,22 +13,24 @@ alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: test_gep_i32
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %1 = MOV64ri32 20
|
||||
# CHECK-NEXT: %2 = LEA64r %0, 1, %1, 0, _
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; CHECK-LABEL: name: test_gep_i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK-NEXT: id: 1, class: gr64_nosp
|
||||
; CHECK-NEXT: id: 2, class: gr64
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 20
|
||||
; CHECK: [[LEA64r:%[0-9]+]] = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, _
|
||||
; CHECK: %rax = COPY [[LEA64r]]
|
||||
; CHECK: RET 0, implicit %rax
|
||||
%0(p0) = COPY %rdi
|
||||
%1(s64) = G_CONSTANT i64 20
|
||||
%2(p0) = G_GEP %0, %1(s64)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -36,27 +37,27 @@
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx0
|
||||
# ALL-LABEL: name: test_insert_128_idx0
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %xmm1
|
||||
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 0
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_128_idx0
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr128x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0
|
||||
; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
|
||||
@ -66,26 +67,26 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx0_undef
|
||||
# ALL-LABEL: name: test_insert_128_idx0_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %1 = COPY %xmm1
|
||||
# ALL-NEXT: undef %2.sub_xmm = COPY %1
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_128_idx0_undef
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vecr
|
||||
; ALL-NEXT: id: 1, class: vr128x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %xmm1
|
||||
; ALL: undef %2.sub_xmm = COPY [[COPY]]
|
||||
; ALL: %zmm0 = COPY %2
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
|
||||
@ -95,27 +96,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx1
|
||||
# ALL-LABEL: name: test_insert_128_idx1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %xmm1
|
||||
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_128_idx1
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr128x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1
|
||||
; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
|
||||
@ -124,27 +125,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx1_undef
|
||||
# ALL-LABEL: name: test_insert_128_idx1_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %1 = COPY %xmm1
|
||||
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_128_idx1_undef
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr128x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %xmm1
|
||||
; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1
|
||||
; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
|
||||
@ -153,27 +154,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx0
|
||||
# ALL-LABEL: name: test_insert_256_idx0
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %ymm1
|
||||
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 0
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_256_idx0
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr256x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0
|
||||
; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
|
||||
@ -183,26 +184,26 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx0_undef
|
||||
# ALL-LABEL: name: test_insert_256_idx0_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %1 = COPY %ymm1
|
||||
# ALL-NEXT: undef %2.sub_ymm = COPY %1
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_256_idx0_undef
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vecr
|
||||
; ALL-NEXT: id: 1, class: vr256x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %ymm1
|
||||
; ALL: undef %2.sub_ymm = COPY [[COPY]]
|
||||
; ALL: %zmm0 = COPY %2
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
|
||||
@ -212,27 +213,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx1
|
||||
# ALL-LABEL: name: test_insert_256_idx1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %ymm1
|
||||
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_256_idx1
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr256x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1
|
||||
; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
|
||||
@ -241,27 +242,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx1_undef
|
||||
# ALL-LABEL: name: test_insert_256_idx1_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %1 = COPY %ymm1
|
||||
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %zmm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; ALL-LABEL: name: test_insert_256_idx1_undef
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr256x
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %ymm1
|
||||
; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1
|
||||
; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=i386-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -8,20 +9,22 @@
|
||||
# Check that we select a the x86.flags.read.u32 intrinsic into a RDFLAGS
|
||||
# instruction. Also check that we constrain the register class of the COPY to
|
||||
# gr32.
|
||||
# CHECK-LABEL: name: read_flags
|
||||
name: read_flags
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = RDFLAGS32
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: read_flags
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr64
|
||||
; CHECK: [[RDFLAGS32_:%[0-9]+]] = RDFLAGS32 implicit-def %esp, implicit %esp
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4
|
||||
; CHECK: %rax = COPY [[SUBREG_TO_REG]]
|
||||
%0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32)
|
||||
%rax = COPY %0(s32)
|
||||
...
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=i586-linux-gnu -mcpu=haswell -mattr=-slow-incdec -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK
|
||||
#
|
||||
# This is necessary to test that attribute-based rule predicates work and that
|
||||
@ -27,15 +28,16 @@ name: const_i32_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i32_1
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV32ri 1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i32_1
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 1
|
||||
; CHECK: %eax = COPY [[MOV32ri]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = G_CONSTANT i32 1
|
||||
%eax = COPY %0(s32)
|
||||
RET 0, implicit %eax
|
||||
@ -45,15 +47,16 @@ name: const_i32_1_optsize
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i32_1_optsize
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV32r1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i32_1_optsize
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK: [[MOV32r1_:%[0-9]+]] = MOV32r1 implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[MOV32r1_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = G_CONSTANT i32 1
|
||||
%eax = COPY %0(s32)
|
||||
RET 0, implicit %eax
|
||||
@ -63,15 +66,16 @@ name: const_i32_1b
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i32_1b
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV32ri 1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i32_1b
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 1
|
||||
; CHECK: %eax = COPY [[MOV32ri]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = G_CONSTANT i32 1
|
||||
%eax = COPY %0(s32)
|
||||
RET 0, implicit %eax
|
||||
@ -81,15 +85,16 @@ name: const_i32_1_optsizeb
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
selected: false
|
||||
# CHECK-LABEL: name: const_i32_1_optsizeb
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
# CHECK: body:
|
||||
# CHECK: %0 = MOV32r1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; CHECK-LABEL: name: const_i32_1_optsizeb
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK: [[MOV32r1_:%[0-9]+]] = MOV32r1 implicit-def %eflags
|
||||
; CHECK: %eax = COPY [[MOV32r1_]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s32) = G_CONSTANT i32 1
|
||||
%eax = COPY %0(s32)
|
||||
RET 0, implicit %eax
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -44,26 +45,26 @@
|
||||
...
|
||||
---
|
||||
name: test_load_i8
|
||||
# ALL-LABEL: name: test_load_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
fixedStack:
|
||||
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %2 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
|
||||
# ALL-NEXT: %al = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_load_i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gpr
|
||||
; ALL-NEXT: id: 2, class: gr8
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV8rm:%[0-9]+]] = MOV8rm [[MOV32rm]], 1, _, 0, _ :: (load 1 from %ir.p1)
|
||||
; ALL: %al = COPY [[MOV8rm]]
|
||||
; ALL: RET 0, implicit %al
|
||||
%1(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
%2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
|
||||
@ -73,26 +74,26 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_load_i16
|
||||
# ALL-LABEL: name: test_load_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
fixedStack:
|
||||
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %2 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
|
||||
# ALL-NEXT: %ax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_load_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gpr
|
||||
; ALL-NEXT: id: 2, class: gr16
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV16rm:%[0-9]+]] = MOV16rm [[MOV32rm]], 1, _, 0, _ :: (load 2 from %ir.p1)
|
||||
; ALL: %ax = COPY [[MOV16rm]]
|
||||
; ALL: RET 0, implicit %ax
|
||||
%1(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
%2(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
|
||||
@ -102,26 +103,26 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_load_i32
|
||||
# ALL-LABEL: name: test_load_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
fixedStack:
|
||||
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %2 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
|
||||
# ALL-NEXT: %eax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_load_i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gpr
|
||||
; ALL-NEXT: id: 2, class: gr32
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.p1)
|
||||
; ALL: %eax = COPY [[MOV32rm1]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%1(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
%2(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
|
||||
@ -131,15 +132,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_store_i8
|
||||
# ALL-LABEL: name: test_store_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -148,13 +143,19 @@ registers:
|
||||
fixedStack:
|
||||
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
|
||||
- { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %1 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
# ALL-NEXT: MOV8mr %1, 1, _, 0, _, %0 :: (store 1 into %ir.p1)
|
||||
# ALL-NEXT: %eax = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_store_i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gpr
|
||||
; ALL-NEXT: id: 3, class: gpr
|
||||
; ALL: [[MOV8rm:%[0-9]+]] = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
; ALL: MOV8mr [[MOV32rm]], 1, _, 0, _, [[MOV8rm]] :: (store 1 into %ir.p1)
|
||||
; ALL: %eax = COPY [[MOV32rm]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%2(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
%0(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
|
||||
%3(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
@ -166,15 +167,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_store_i16
|
||||
# ALL-LABEL: name: test_store_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -183,13 +178,19 @@ registers:
|
||||
fixedStack:
|
||||
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
|
||||
- { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %1 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
# ALL-NEXT: MOV16mr %1, 1, _, 0, _, %0 :: (store 2 into %ir.p1)
|
||||
# ALL-NEXT: %eax = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_store_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr16
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gpr
|
||||
; ALL-NEXT: id: 3, class: gpr
|
||||
; ALL: [[MOV16rm:%[0-9]+]] = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
; ALL: MOV16mr [[MOV32rm]], 1, _, 0, _, [[MOV16rm]] :: (store 2 into %ir.p1)
|
||||
; ALL: %eax = COPY [[MOV32rm]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%2(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
%0(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
|
||||
%3(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
@ -201,15 +202,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_store_i32
|
||||
# ALL-LABEL: name: test_store_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -218,13 +213,19 @@ registers:
|
||||
fixedStack:
|
||||
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
|
||||
- { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %1 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
# ALL-NEXT: MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
|
||||
# ALL-NEXT: %eax = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_store_i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gpr
|
||||
; ALL-NEXT: id: 3, class: gpr
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
; ALL: MOV32mr [[MOV32rm1]], 1, _, 0, _, [[MOV32rm]] :: (store 4 into %ir.p1)
|
||||
; ALL: %eax = COPY [[MOV32rm1]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%2(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
%0(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
%3(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
@ -236,26 +237,26 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_load_ptr
|
||||
# ALL-LABEL: name: test_load_ptr
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
fixedStack:
|
||||
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %2 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.ptr1)
|
||||
# ALL-NEXT: %eax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_load_ptr
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gpr
|
||||
; ALL-NEXT: id: 2, class: gr32
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.ptr1)
|
||||
; ALL: %eax = COPY [[MOV32rm1]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%1(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
%2(p0) = G_LOAD %0(p0) :: (load 4 from %ir.ptr1)
|
||||
@ -265,15 +266,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_store_ptr
|
||||
# ALL-LABEL: name: test_store_ptr
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gpr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: gpr, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
@ -282,12 +277,18 @@ registers:
|
||||
fixedStack:
|
||||
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
|
||||
- { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
|
||||
# ALL: %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
# ALL-NEXT: %1 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
# ALL-NEXT: MOV32mr %0, 1, _, 0, _, %1 :: (store 4 into %ir.ptr1)
|
||||
# ALL-NEXT: RET 0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test_store_ptr
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gpr
|
||||
; ALL-NEXT: id: 3, class: gpr
|
||||
; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
|
||||
; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
; ALL: MOV32mr [[MOV32rm]], 1, _, 0, _, [[MOV32rm1]] :: (store 4 into %ir.ptr1)
|
||||
; ALL: RET 0
|
||||
%2(p0) = G_FRAME_INDEX %fixed-stack.1
|
||||
%0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
|
||||
%3(p0) = G_FRAME_INDEX %fixed-stack.0
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F
|
||||
--- |
|
||||
define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) {
|
||||
@ -23,24 +24,24 @@
|
||||
...
|
||||
---
|
||||
name: test_load_v16i32_noalign
|
||||
# AVX512F-LABEL: name: test_load_v16i32_noalign
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX512F: registers:
|
||||
# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: vecr }
|
||||
# AVX512F: %0 = COPY %rdi
|
||||
# AVX512F-NEXT: %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
|
||||
# AVX512F-NEXT: %zmm0 = COPY %1
|
||||
# AVX512F-NEXT: RET 0, implicit %zmm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; AVX512F-LABEL: name: test_load_v16i32_noalign
|
||||
; AVX512F: registers:
|
||||
; AVX512F-NEXT: id: 0, class: gr64
|
||||
; AVX512F-NEXT: id: 1, class: vr512
|
||||
; AVX512F: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; AVX512F: [[VMOVUPSZrm:%[0-9]+]] = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
|
||||
; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
|
||||
; AVX512F: RET 0, implicit %zmm0
|
||||
%0(p0) = COPY %rdi
|
||||
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
|
||||
%zmm0 = COPY %1(<16 x s32>)
|
||||
@ -49,24 +50,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_load_v16i32_align
|
||||
# AVX512F-LABEL: name: test_load_v16i32_align
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX512F: registers:
|
||||
# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: vecr }
|
||||
# AVX512F: %0 = COPY %rdi
|
||||
# AVX512F-NEXT: %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
|
||||
# AVX512F-NEXT: %zmm0 = COPY %1
|
||||
# AVX512F-NEXT: RET 0, implicit %zmm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; AVX512F-LABEL: name: test_load_v16i32_align
|
||||
; AVX512F: registers:
|
||||
; AVX512F-NEXT: id: 0, class: gr64
|
||||
; AVX512F-NEXT: id: 1, class: vr512
|
||||
; AVX512F: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; AVX512F: [[VMOVUPSZrm:%[0-9]+]] = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
|
||||
; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
|
||||
; AVX512F: RET 0, implicit %zmm0
|
||||
%0(p0) = COPY %rdi
|
||||
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
|
||||
%zmm0 = COPY %1(<16 x s32>)
|
||||
@ -75,24 +76,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_store_v16i32_noalign
|
||||
# AVX512F-LABEL: name: test_store_v16i32_noalign
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX512F: registers:
|
||||
# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: gpr }
|
||||
# AVX512F: %0 = COPY %zmm0
|
||||
# AVX512F-NEXT: %1 = COPY %rdi
|
||||
# AVX512F-NEXT: VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 1)
|
||||
# AVX512F-NEXT: RET 0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %zmm0
|
||||
|
||||
; AVX512F-LABEL: name: test_store_v16i32_noalign
|
||||
; AVX512F: registers:
|
||||
; AVX512F-NEXT: id: 0, class: vr512
|
||||
; AVX512F-NEXT: id: 1, class: gr64
|
||||
; AVX512F: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; AVX512F: [[COPY1:%[0-9]+]] = COPY %rdi
|
||||
; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 1)
|
||||
; AVX512F: RET 0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(p0) = COPY %rdi
|
||||
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
|
||||
@ -101,24 +102,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_store_v16i32_align
|
||||
# AVX512F-LABEL: name: test_store_v16i32_align
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX512F: registers:
|
||||
# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: gpr }
|
||||
# AVX512F: %0 = COPY %zmm0
|
||||
# AVX512F-NEXT: %1 = COPY %rdi
|
||||
# AVX512F-NEXT: VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 32)
|
||||
# AVX512F-NEXT: RET 0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %zmm0
|
||||
|
||||
; AVX512F-LABEL: name: test_store_v16i32_align
|
||||
; AVX512F: registers:
|
||||
; AVX512F-NEXT: id: 0, class: vr512
|
||||
; AVX512F-NEXT: id: 1, class: gr64
|
||||
; AVX512F: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; AVX512F: [[COPY1:%[0-9]+]] = COPY %rdi
|
||||
; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 32)
|
||||
; AVX512F: RET 0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(p0) = COPY %rdi
|
||||
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
|
||||
--- |
|
||||
@ -7,42 +8,42 @@
|
||||
...
|
||||
---
|
||||
name: test_merge
|
||||
# AVX-LABEL: name: test_merge
|
||||
#
|
||||
# AVX512VL-LABEL: name: test_merge
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX: registers:
|
||||
# AVX-NEXT: - { id: 0, class: vr128, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 1, class: vr256, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 3, class: vr256, preferred-register: '' }
|
||||
#
|
||||
# AVX512VL: registers:
|
||||
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 3, class: vr256x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
# AVX: %0 = IMPLICIT_DEF
|
||||
# AVX-NEXT: undef %2.sub_xmm = COPY %0
|
||||
# AVX-NEXT: %3 = VINSERTF128rr %2, %0, 1
|
||||
# AVX-NEXT: %1 = COPY %3
|
||||
# AVX-NEXT: %ymm0 = COPY %1
|
||||
# AVX-NEXT: RET 0, implicit %ymm0
|
||||
#
|
||||
# AVX512VL: %0 = IMPLICIT_DEF
|
||||
# AVX512VL-NEXT: undef %2.sub_xmm = COPY %0
|
||||
# AVX512VL-NEXT: %3 = VINSERTF32x4Z256rr %2, %0, 1
|
||||
# AVX512VL-NEXT: %1 = COPY %3
|
||||
# AVX512VL-NEXT: %ymm0 = COPY %1
|
||||
# AVX512VL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
|
||||
; AVX-LABEL: name: test_merge
|
||||
; AVX: registers:
|
||||
; AVX-NEXT: id: 0, class: vr128
|
||||
; AVX-NEXT: id: 1, class: vr256
|
||||
; AVX-NEXT: id: 2, class: vr256
|
||||
; AVX-NEXT: id: 3, class: vr256
|
||||
; AVX: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; AVX: undef %2.sub_xmm = COPY [[DEF]]
|
||||
; AVX: [[VINSERTF128rr:%[0-9]+]] = VINSERTF128rr %2, [[DEF]], 1
|
||||
; AVX: [[COPY:%[0-9]+]] = COPY [[VINSERTF128rr]]
|
||||
; AVX: %ymm0 = COPY [[COPY]]
|
||||
; AVX: RET 0, implicit %ymm0
|
||||
; AVX512VL-LABEL: name: test_merge
|
||||
; AVX512VL: registers:
|
||||
; AVX512VL-NEXT: id: 0, class: vr128x
|
||||
; AVX512VL-NEXT: id: 1, class: vr256x
|
||||
; AVX512VL-NEXT: id: 2, class: vr256x
|
||||
; AVX512VL-NEXT: id: 3, class: vr256x
|
||||
; AVX512VL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; AVX512VL: undef %2.sub_xmm = COPY [[DEF]]
|
||||
; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]] = VINSERTF32x4Z256rr %2, [[DEF]], 1
|
||||
; AVX512VL: [[COPY:%[0-9]+]] = COPY [[VINSERTF32x4Z256rr]]
|
||||
; AVX512VL: %ymm0 = COPY [[COPY]]
|
||||
; AVX512VL: RET 0, implicit %ymm0
|
||||
%0(<4 x s32>) = IMPLICIT_DEF
|
||||
%1(<8 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>)
|
||||
%ymm0 = COPY %1(<8 x s32>)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
--- |
|
||||
define void @test_merge_v128() {
|
||||
@ -11,31 +12,31 @@
|
||||
...
|
||||
---
|
||||
name: test_merge_v128
|
||||
# ALL-LABEL: name: test_merge_v128
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 4, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 5, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: undef %2.sub_xmm = COPY %0
|
||||
# ALL-NEXT: %3 = VINSERTF32x4Zrr %2, %0, 1
|
||||
# ALL-NEXT: %4 = VINSERTF32x4Zrr %3, %0, 2
|
||||
# ALL-NEXT: %5 = VINSERTF32x4Zrr %4, %0, 3
|
||||
# ALL-NEXT: %1 = COPY %5
|
||||
# ALL-NEXT: %zmm0 = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %zmm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
|
||||
; ALL-LABEL: name: test_merge_v128
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr128x
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL-NEXT: id: 3, class: vr512
|
||||
; ALL-NEXT: id: 4, class: vr512
|
||||
; ALL-NEXT: id: 5, class: vr512
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: undef %2.sub_xmm = COPY [[DEF]]
|
||||
; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr %2, [[DEF]], 1
|
||||
; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]] = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
|
||||
; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]] = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY [[VINSERTF32x4Zrr2]]
|
||||
; ALL: %zmm0 = COPY [[COPY]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<4 x s32>) = IMPLICIT_DEF
|
||||
%1(<16 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>)
|
||||
%zmm0 = COPY %1(<16 x s32>)
|
||||
@ -44,27 +45,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_merge_v256
|
||||
# ALL-LABEL: name: test_merge_v256
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: undef %2.sub_ymm = COPY %0
|
||||
# ALL-NEXT: %3 = VINSERTF64x4Zrr %2, %0, 1
|
||||
# ALL-NEXT: %1 = COPY %3
|
||||
# ALL-NEXT: %zmm0 = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %zmm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
|
||||
; ALL-LABEL: name: test_merge_v256
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr256x
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL-NEXT: id: 3, class: vr512
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: undef %2.sub_ymm = COPY [[DEF]]
|
||||
; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr %2, [[DEF]], 1
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY [[VINSERTF64x4Zrr]]
|
||||
; ALL: %zmm0 = COPY [[COPY]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<8 x s32>) = IMPLICIT_DEF
|
||||
%1(<16 x s32>) = G_MERGE_VALUES %0(<8 x s32>), %0(<8 x s32>)
|
||||
%zmm0 = COPY %1(<16 x s32>)
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
|
||||
@ -19,28 +20,27 @@
|
||||
...
|
||||
---
|
||||
name: test_mul_i16
|
||||
# ALL-LABEL: name: test_mul_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: body: |
|
||||
# ALL: %0 = COPY %di
|
||||
# ALL-NEXT: %1 = COPY %si
|
||||
# ALL-NEXT: %2 = IMUL16rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %ax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_mul_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr16
|
||||
; ALL-NEXT: id: 1, class: gr16
|
||||
; ALL-NEXT: id: 2, class: gr16
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %di
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %si
|
||||
; ALL: [[IMUL16rr:%[0-9]+]] = IMUL16rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %ax = COPY [[IMUL16rr]]
|
||||
; ALL: RET 0, implicit %ax
|
||||
%0(s16) = COPY %di
|
||||
%1(s16) = COPY %si
|
||||
%2(s16) = G_MUL %0, %1
|
||||
@ -50,28 +50,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_i32
|
||||
# ALL-LABEL: name: test_mul_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: body: |
|
||||
# ALL: %0 = COPY %edi
|
||||
# ALL-NEXT: %1 = COPY %esi
|
||||
# ALL-NEXT: %2 = IMUL32rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %eax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_mul_i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gr32
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; ALL: [[IMUL32rr:%[0-9]+]] = IMUL32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %eax = COPY [[IMUL32rr]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s32) = G_MUL %0, %1
|
||||
@ -81,28 +80,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_i64
|
||||
# ALL-LABEL: name: test_mul_i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
- { id: 2, class: gpr }
|
||||
# ALL: body: |
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %rsi
|
||||
# ALL-NEXT: %2 = IMUL64rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %rsi
|
||||
|
||||
; ALL-LABEL: name: test_mul_i64
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64
|
||||
; ALL-NEXT: id: 1, class: gr64
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
|
||||
; ALL: [[IMUL64rr:%[0-9]+]] = IMUL64rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %rax = COPY [[IMUL64rr]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s64) = COPY %rsi
|
||||
%2(s64) = G_MUL %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
@ -90,23 +91,27 @@
|
||||
...
|
||||
---
|
||||
name: test_mul_v8i16
|
||||
# CHECK-LABEL: name: test_mul_v8i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = PMULLWrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v8i16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128
|
||||
; CHECK-NEXT: id: 1, class: vr128
|
||||
; CHECK-NEXT: id: 2, class: vr128
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[PMULLWrr:%[0-9]+]] = PMULLWrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[PMULLWrr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<8 x s16>) = COPY %xmm0
|
||||
%1(<8 x s16>) = COPY %xmm1
|
||||
%2(<8 x s16>) = G_MUL %0, %1
|
||||
@ -116,23 +121,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v8i16_avx
|
||||
# CHECK-LABEL: name: test_mul_v8i16_avx
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLWrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v8i16_avx
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128
|
||||
; CHECK-NEXT: id: 1, class: vr128
|
||||
; CHECK-NEXT: id: 2, class: vr128
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[VPMULLWrr:%[0-9]+]] = VPMULLWrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[VPMULLWrr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<8 x s16>) = COPY %xmm0
|
||||
%1(<8 x s16>) = COPY %xmm1
|
||||
%2(<8 x s16>) = G_MUL %0, %1
|
||||
@ -142,23 +151,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v8i16_avx512bwvl
|
||||
# CHECK-LABEL: name: test_mul_v8i16_avx512bwvl
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLWZ128rr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v8i16_avx512bwvl
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128x
|
||||
; CHECK-NEXT: id: 1, class: vr128x
|
||||
; CHECK-NEXT: id: 2, class: vr128x
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[VPMULLWZ128rr:%[0-9]+]] = VPMULLWZ128rr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[VPMULLWZ128rr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<8 x s16>) = COPY %xmm0
|
||||
%1(<8 x s16>) = COPY %xmm1
|
||||
%2(<8 x s16>) = G_MUL %0, %1
|
||||
@ -168,23 +181,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v4i32
|
||||
# CHECK-LABEL: name: test_mul_v4i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = PMULLDrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v4i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128
|
||||
; CHECK-NEXT: id: 1, class: vr128
|
||||
; CHECK-NEXT: id: 2, class: vr128
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[PMULLDrr:%[0-9]+]] = PMULLDrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[PMULLDrr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<4 x s32>) = COPY %xmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<4 x s32>) = G_MUL %0, %1
|
||||
@ -194,23 +211,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v4i32_avx
|
||||
# CHECK-LABEL: name: test_mul_v4i32_avx
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLDrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v4i32_avx
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128
|
||||
; CHECK-NEXT: id: 1, class: vr128
|
||||
; CHECK-NEXT: id: 2, class: vr128
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[VPMULLDrr:%[0-9]+]] = VPMULLDrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[VPMULLDrr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<4 x s32>) = COPY %xmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<4 x s32>) = G_MUL %0, %1
|
||||
@ -220,23 +241,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v4i32_avx512vl
|
||||
# CHECK-LABEL: name: test_mul_v4i32_avx512vl
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLDZ128rr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v4i32_avx512vl
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128x
|
||||
; CHECK-NEXT: id: 1, class: vr128x
|
||||
; CHECK-NEXT: id: 2, class: vr128x
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[VPMULLDZ128rr:%[0-9]+]] = VPMULLDZ128rr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[VPMULLDZ128rr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<4 x s32>) = COPY %xmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<4 x s32>) = G_MUL %0, %1
|
||||
@ -246,23 +271,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v2i64
|
||||
# CHECK-LABEL: name: test_mul_v2i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLQZ128rr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %xmm0, %xmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v2i64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr128x
|
||||
; CHECK-NEXT: id: 1, class: vr128x
|
||||
; CHECK-NEXT: id: 2, class: vr128x
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
|
||||
; CHECK: [[VPMULLQZ128rr:%[0-9]+]] = VPMULLQZ128rr [[COPY]], [[COPY1]]
|
||||
; CHECK: %xmm0 = COPY [[VPMULLQZ128rr]]
|
||||
; CHECK: RET 0, implicit %xmm0
|
||||
%0(<2 x s64>) = COPY %xmm0
|
||||
%1(<2 x s64>) = COPY %xmm1
|
||||
%2(<2 x s64>) = G_MUL %0, %1
|
||||
@ -272,23 +301,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v16i16
|
||||
# CHECK-LABEL: name: test_mul_v16i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLWYrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v16i16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr256
|
||||
; CHECK-NEXT: id: 1, class: vr256
|
||||
; CHECK-NEXT: id: 2, class: vr256
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; CHECK: [[VPMULLWYrr:%[0-9]+]] = VPMULLWYrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %ymm0 = COPY [[VPMULLWYrr]]
|
||||
; CHECK: RET 0, implicit %ymm0
|
||||
%0(<16 x s16>) = COPY %ymm0
|
||||
%1(<16 x s16>) = COPY %ymm1
|
||||
%2(<16 x s16>) = G_MUL %0, %1
|
||||
@ -298,23 +331,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v16i16_avx512bwvl
|
||||
# CHECK-LABEL: name: test_mul_v16i16_avx512bwvl
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLWZ256rr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v16i16_avx512bwvl
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr256x
|
||||
; CHECK-NEXT: id: 1, class: vr256x
|
||||
; CHECK-NEXT: id: 2, class: vr256x
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; CHECK: [[VPMULLWZ256rr:%[0-9]+]] = VPMULLWZ256rr [[COPY]], [[COPY1]]
|
||||
; CHECK: %ymm0 = COPY [[VPMULLWZ256rr]]
|
||||
; CHECK: RET 0, implicit %ymm0
|
||||
%0(<16 x s16>) = COPY %ymm0
|
||||
%1(<16 x s16>) = COPY %ymm1
|
||||
%2(<16 x s16>) = G_MUL %0, %1
|
||||
@ -324,23 +361,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v8i32
|
||||
# CHECK-LABEL: name: test_mul_v8i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLDYrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v8i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr256
|
||||
; CHECK-NEXT: id: 1, class: vr256
|
||||
; CHECK-NEXT: id: 2, class: vr256
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; CHECK: [[VPMULLDYrr:%[0-9]+]] = VPMULLDYrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %ymm0 = COPY [[VPMULLDYrr]]
|
||||
; CHECK: RET 0, implicit %ymm0
|
||||
%0(<8 x s32>) = COPY %ymm0
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<8 x s32>) = G_MUL %0, %1
|
||||
@ -350,23 +391,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v8i32_avx512vl
|
||||
# CHECK-LABEL: name: test_mul_v8i32_avx512vl
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLDZ256rr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v8i32_avx512vl
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr256x
|
||||
; CHECK-NEXT: id: 1, class: vr256x
|
||||
; CHECK-NEXT: id: 2, class: vr256x
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; CHECK: [[VPMULLDZ256rr:%[0-9]+]] = VPMULLDZ256rr [[COPY]], [[COPY1]]
|
||||
; CHECK: %ymm0 = COPY [[VPMULLDZ256rr]]
|
||||
; CHECK: RET 0, implicit %ymm0
|
||||
%0(<8 x s32>) = COPY %ymm0
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<8 x s32>) = G_MUL %0, %1
|
||||
@ -376,23 +421,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v4i64
|
||||
# CHECK-LABEL: name: test_mul_v4i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLQZ256rr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v4i64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr256x
|
||||
; CHECK-NEXT: id: 1, class: vr256x
|
||||
; CHECK-NEXT: id: 2, class: vr256x
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
|
||||
; CHECK: [[VPMULLQZ256rr:%[0-9]+]] = VPMULLQZ256rr [[COPY]], [[COPY1]]
|
||||
; CHECK: %ymm0 = COPY [[VPMULLQZ256rr]]
|
||||
; CHECK: RET 0, implicit %ymm0
|
||||
%0(<4 x s64>) = COPY %ymm0
|
||||
%1(<4 x s64>) = COPY %ymm1
|
||||
%2(<4 x s64>) = G_MUL %0, %1
|
||||
@ -402,23 +451,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v32i16
|
||||
# CHECK-LABEL: name: test_mul_v32i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLWZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v32i16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr512
|
||||
; CHECK-NEXT: id: 1, class: vr512
|
||||
; CHECK-NEXT: id: 2, class: vr512
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; CHECK: [[VPMULLWZrr:%[0-9]+]] = VPMULLWZrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %zmm0 = COPY [[VPMULLWZrr]]
|
||||
; CHECK: RET 0, implicit %zmm0
|
||||
%0(<32 x s16>) = COPY %zmm0
|
||||
%1(<32 x s16>) = COPY %zmm1
|
||||
%2(<32 x s16>) = G_MUL %0, %1
|
||||
@ -428,23 +481,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v16i32
|
||||
# CHECK-LABEL: name: test_mul_v16i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLDZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v16i32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr512
|
||||
; CHECK-NEXT: id: 1, class: vr512
|
||||
; CHECK-NEXT: id: 2, class: vr512
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; CHECK: [[VPMULLDZrr:%[0-9]+]] = VPMULLDZrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %zmm0 = COPY [[VPMULLDZrr]]
|
||||
; CHECK: RET 0, implicit %zmm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<16 x s32>) = COPY %zmm1
|
||||
%2(<16 x s32>) = G_MUL %0, %1
|
||||
@ -454,23 +511,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_mul_v8i64
|
||||
# CHECK-LABEL: name: test_mul_v8i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# CHECK: %2 = VPMULLQZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; CHECK-LABEL: name: test_mul_v8i64
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: vr512
|
||||
; CHECK-NEXT: id: 1, class: vr512
|
||||
; CHECK-NEXT: id: 2, class: vr512
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; CHECK: [[VPMULLQZrr:%[0-9]+]] = VPMULLQZrr [[COPY]], [[COPY1]]
|
||||
; CHECK: %zmm0 = COPY [[VPMULLQZrr]]
|
||||
; CHECK: RET 0, implicit %zmm0
|
||||
%0(<8 x s64>) = COPY %zmm0
|
||||
%1(<8 x s64>) = COPY %zmm1
|
||||
%2(<8 x s64>) = G_MUL %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -24,14 +25,9 @@
|
||||
...
|
||||
---
|
||||
name: test_or_i8
|
||||
# ALL-LABEL: name: test_or_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -40,15 +36,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %dil
|
||||
# ALL-NEXT: %1 = COPY %sil
|
||||
# ALL-NEXT: %2 = OR8rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %al = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_or_i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr8
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %sil
|
||||
; ALL: [[OR8rr:%[0-9]+]] = OR8rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %al = COPY [[OR8rr]]
|
||||
; ALL: RET 0, implicit %al
|
||||
%0(s8) = COPY %dil
|
||||
%1(s8) = COPY %sil
|
||||
%2(s8) = G_OR %0, %1
|
||||
@ -58,14 +59,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_or_i16
|
||||
# ALL-LABEL: name: test_or_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -74,15 +70,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %di
|
||||
# ALL-NEXT: %1 = COPY %si
|
||||
# ALL-NEXT: %2 = OR16rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %ax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_or_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr16
|
||||
; ALL-NEXT: id: 1, class: gr16
|
||||
; ALL-NEXT: id: 2, class: gr16
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %di
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %si
|
||||
; ALL: [[OR16rr:%[0-9]+]] = OR16rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %ax = COPY [[OR16rr]]
|
||||
; ALL: RET 0, implicit %ax
|
||||
%0(s16) = COPY %di
|
||||
%1(s16) = COPY %si
|
||||
%2(s16) = G_OR %0, %1
|
||||
@ -92,14 +93,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_or_i32
|
||||
# ALL-LABEL: name: test_or_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -108,15 +104,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %edi
|
||||
# ALL-NEXT: %1 = COPY %esi
|
||||
# ALL-NEXT: %2 = OR32rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %eax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_or_i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gr32
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; ALL: [[OR32rr:%[0-9]+]] = OR32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %eax = COPY [[OR32rr]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s32) = G_OR %0, %1
|
||||
@ -126,14 +127,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_or_i64
|
||||
# ALL-LABEL: name: test_or_i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -142,15 +138,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %rsi
|
||||
# ALL-NEXT: %2 = OR64rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %rsi
|
||||
|
||||
; ALL-LABEL: name: test_or_i64
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64
|
||||
; ALL-NEXT: id: 1, class: gr64
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
|
||||
; ALL: [[OR64rr:%[0-9]+]] = OR64rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %rax = COPY [[OR64rr]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s64) = COPY %rsi
|
||||
%2(s64) = G_OR %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -26,23 +27,27 @@
|
||||
...
|
||||
---
|
||||
name: test_sub_v64i8
|
||||
# ALL-LABEL: name: test_sub_v64i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPSUBBZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_sub_v64i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPSUBBZrr:%[0-9]+]] = VPSUBBZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPSUBBZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<64 x s8>) = COPY %zmm0
|
||||
%1(<64 x s8>) = COPY %zmm1
|
||||
%2(<64 x s8>) = G_SUB %0, %1
|
||||
@ -52,23 +57,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_sub_v32i16
|
||||
# ALL-LABEL: name: test_sub_v32i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPSUBWZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_sub_v32i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPSUBWZrr:%[0-9]+]] = VPSUBWZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPSUBWZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<32 x s16>) = COPY %zmm0
|
||||
%1(<32 x s16>) = COPY %zmm1
|
||||
%2(<32 x s16>) = G_SUB %0, %1
|
||||
@ -78,23 +87,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_sub_v16i32
|
||||
# ALL-LABEL: name: test_sub_v16i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPSUBDZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_sub_v16i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPSUBDZrr:%[0-9]+]] = VPSUBDZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPSUBDZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<16 x s32>) = COPY %zmm1
|
||||
%2(<16 x s32>) = G_SUB %0, %1
|
||||
@ -104,23 +117,27 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_sub_v8i64
|
||||
# ALL-LABEL: name: test_sub_v8i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %2 = VPSUBQZrr %0, %1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %zmm1
|
||||
|
||||
; ALL-LABEL: name: test_sub_v8i64
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr512
|
||||
; ALL-NEXT: id: 2, class: vr512
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
|
||||
; ALL: [[VPSUBQZrr:%[0-9]+]] = VPSUBQZrr [[COPY]], [[COPY1]]
|
||||
; ALL: %zmm0 = COPY [[VPSUBQZrr]]
|
||||
; ALL: RET 0, implicit %zmm0
|
||||
%0(<8 x s64>) = COPY %zmm0
|
||||
%1(<8 x s64>) = COPY %zmm1
|
||||
%2(<8 x s64>) = G_SUB %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
|
||||
--- |
|
||||
define i1 @trunc_i32toi1(i32 %a) {
|
||||
@ -33,24 +34,24 @@
|
||||
...
|
||||
---
|
||||
name: trunc_i32toi1
|
||||
# CHECK-LABEL: name: trunc_i32toi1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %0.sub_8bit
|
||||
# CHECK-NEXT: %al = COPY %1
|
||||
# CHECK-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: trunc_i32toi1
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr8
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
|
||||
; CHECK: %al = COPY [[COPY1]]
|
||||
; CHECK: RET 0, implicit %al
|
||||
%0(s32) = COPY %edi
|
||||
%1(s1) = G_TRUNC %0(s32)
|
||||
%al = COPY %1(s1)
|
||||
@ -59,24 +60,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: trunc_i32toi8
|
||||
# CHECK-LABEL: name: trunc_i32toi8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %0.sub_8bit
|
||||
# CHECK-NEXT: %al = COPY %1
|
||||
# CHECK-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: trunc_i32toi8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr8
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
|
||||
; CHECK: %al = COPY [[COPY1]]
|
||||
; CHECK: RET 0, implicit %al
|
||||
%0(s32) = COPY %edi
|
||||
%1(s8) = G_TRUNC %0(s32)
|
||||
%al = COPY %1(s8)
|
||||
@ -85,24 +86,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: trunc_i32toi16
|
||||
# CHECK-LABEL: name: trunc_i32toi16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: %0 = COPY %edi
|
||||
# CHECK-NEXT: %1 = COPY %0.sub_16bit
|
||||
# CHECK-NEXT: %ax = COPY %1
|
||||
# CHECK-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; CHECK-LABEL: name: trunc_i32toi16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr32
|
||||
; CHECK-NEXT: id: 1, class: gr16
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
|
||||
; CHECK: %ax = COPY [[COPY1]]
|
||||
; CHECK: RET 0, implicit %ax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s16) = G_TRUNC %0(s32)
|
||||
%ax = COPY %1(s16)
|
||||
@ -111,24 +112,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: trunc_i64toi8
|
||||
# CHECK-LABEL: name: trunc_i64toi8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: %0 = COPY %rdi
|
||||
# CHECK-NEXT: %1 = COPY %0.sub_8bit
|
||||
# CHECK-NEXT: %al = COPY %1
|
||||
# CHECK-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; CHECK-LABEL: name: trunc_i64toi8
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64_with_sub_8bit
|
||||
; CHECK-NEXT: id: 1, class: gr8
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
|
||||
; CHECK: %al = COPY [[COPY1]]
|
||||
; CHECK: RET 0, implicit %al
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s8) = G_TRUNC %0(s64)
|
||||
%al = COPY %1(s8)
|
||||
@ -137,24 +138,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: trunc_i64toi16
|
||||
# CHECK-LABEL: name: trunc_i64toi16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: %0 = COPY %rdi
|
||||
# CHECK-NEXT: %1 = COPY %0.sub_16bit
|
||||
# CHECK-NEXT: %ax = COPY %1
|
||||
# CHECK-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; CHECK-LABEL: name: trunc_i64toi16
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK-NEXT: id: 1, class: gr16
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
|
||||
; CHECK: %ax = COPY [[COPY1]]
|
||||
; CHECK: RET 0, implicit %ax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s16) = G_TRUNC %0(s64)
|
||||
%ax = COPY %1(s16)
|
||||
@ -163,24 +164,24 @@ body: |
|
||||
...
|
||||
---
|
||||
name: trunc_i64toi32
|
||||
# CHECK-LABEL: name: trunc_i64toi32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# CHECK: registers:
|
||||
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
# CHECK: %0 = COPY %rdi
|
||||
# CHECK-NEXT: %1 = COPY %0.sub_32bit
|
||||
# CHECK-NEXT: %eax = COPY %1
|
||||
# CHECK-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi
|
||||
|
||||
; CHECK-LABEL: name: trunc_i64toi32
|
||||
; CHECK: registers:
|
||||
; CHECK-NEXT: id: 0, class: gr64
|
||||
; CHECK-NEXT: id: 1, class: gr32
|
||||
; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32bit
|
||||
; CHECK: %eax = COPY [[COPY1]]
|
||||
; CHECK: RET 0, implicit %eax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s32) = G_TRUNC %0(s64)
|
||||
%eax = COPY %1(s32)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
--- |
|
||||
|
||||
@ -13,23 +14,23 @@
|
||||
...
|
||||
---
|
||||
name: test
|
||||
# ALL-LABEL: name: test
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %al = COPY %0
|
||||
# ALL-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
; ALL-LABEL: name: test
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: %al = COPY [[DEF]]
|
||||
; ALL: RET 0, implicit %al
|
||||
%0(s8) = G_IMPLICIT_DEF
|
||||
%al = COPY %0(s8)
|
||||
RET 0, implicit %al
|
||||
@ -37,14 +38,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test2
|
||||
# ALL-LABEL: name: test2
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -53,15 +49,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %dil
|
||||
# ALL-NEXT: %1 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %2 = ADD8rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %al = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi
|
||||
|
||||
; ALL-LABEL: name: test2
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr8
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: [[ADD8rr:%[0-9]+]] = ADD8rr [[COPY]], [[DEF]], implicit-def %eflags
|
||||
; ALL: %al = COPY [[ADD8rr]]
|
||||
; ALL: RET 0, implicit %al
|
||||
%0(s8) = COPY %dil
|
||||
%1(s8) = G_IMPLICIT_DEF
|
||||
%2(s8) = G_ADD %0, %1
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
|
||||
--- |
|
||||
@ -8,41 +9,41 @@
|
||||
...
|
||||
---
|
||||
name: test_unmerge
|
||||
# AVX-LABEL: name: test_unmerge
|
||||
#
|
||||
# AVX512VL-LABEL: name: test_unmerge
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX: registers:
|
||||
# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 2, class: vr128, preferred-register: '' }
|
||||
#
|
||||
# AVX512VL: registers:
|
||||
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# AVX: %0 = IMPLICIT_DEF
|
||||
# AVX-NEXT: %1 = COPY %0.sub_xmm
|
||||
# AVX-NEXT: %2 = VEXTRACTF128rr %0, 1
|
||||
# AVX-NEXT: %xmm0 = COPY %1
|
||||
# AVX-NEXT: %xmm1 = COPY %2
|
||||
# AVX-NEXT: RET 0, implicit %xmm0, implicit %xmm1
|
||||
#
|
||||
# AVX512VL: %0 = IMPLICIT_DEF
|
||||
# AVX512VL-NEXT: %1 = COPY %0.sub_xmm
|
||||
# AVX512VL-NEXT: %2 = VEXTRACTF32x4Z256rr %0, 1
|
||||
# AVX512VL-NEXT: %xmm0 = COPY %1
|
||||
# AVX512VL-NEXT: %xmm1 = COPY %2
|
||||
# AVX512VL-NEXT: RET 0, implicit %xmm0, implicit %xmm1
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
|
||||
; AVX-LABEL: name: test_unmerge
|
||||
; AVX: registers:
|
||||
; AVX-NEXT: id: 0, class: vr256
|
||||
; AVX-NEXT: id: 1, class: vr128
|
||||
; AVX-NEXT: id: 2, class: vr128
|
||||
; AVX: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; AVX: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
|
||||
; AVX: [[VEXTRACTF128rr:%[0-9]+]] = VEXTRACTF128rr [[DEF]], 1
|
||||
; AVX: %xmm0 = COPY [[COPY]]
|
||||
; AVX: %xmm1 = COPY [[VEXTRACTF128rr]]
|
||||
; AVX: RET 0, implicit %xmm0, implicit %xmm1
|
||||
; AVX512VL-LABEL: name: test_unmerge
|
||||
; AVX512VL: registers:
|
||||
; AVX512VL-NEXT: id: 0, class: vr256x
|
||||
; AVX512VL-NEXT: id: 1, class: vr128x
|
||||
; AVX512VL-NEXT: id: 2, class: vr128x
|
||||
; AVX512VL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; AVX512VL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
|
||||
; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]] = VEXTRACTF32x4Z256rr [[DEF]], 1
|
||||
; AVX512VL: %xmm0 = COPY [[COPY]]
|
||||
; AVX512VL: %xmm1 = COPY [[VEXTRACTF32x4Z256rr]]
|
||||
; AVX512VL: RET 0, implicit %xmm0, implicit %xmm1
|
||||
%0(<8 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>), %2(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
|
||||
%xmm0 = COPY %1(<4 x s32>)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
--- |
|
||||
define void @test_unmerge_v128() {
|
||||
@ -11,32 +12,32 @@
|
||||
...
|
||||
---
|
||||
name: test_unmerge_v128
|
||||
# ALL-LABEL: name: test_unmerge_v128
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 3, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 4, class: vr128x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
- { id: 3, class: vecr }
|
||||
- { id: 4, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %1 = COPY %0.sub_xmm
|
||||
# ALL-NEXT: %2 = VEXTRACTF32x4Zrr %0, 1
|
||||
# ALL-NEXT: %3 = VEXTRACTF32x4Zrr %0, 2
|
||||
# ALL-NEXT: %4 = VEXTRACTF32x4Zrr %0, 3
|
||||
# ALL-NEXT: %xmm0 = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %xmm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
|
||||
; ALL-LABEL: name: test_unmerge_v128
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr128x
|
||||
; ALL-NEXT: id: 2, class: vr128x
|
||||
; ALL-NEXT: id: 3, class: vr128x
|
||||
; ALL-NEXT: id: 4, class: vr128x
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
|
||||
; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 1
|
||||
; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 2
|
||||
; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 3
|
||||
; ALL: %xmm0 = COPY [[COPY]]
|
||||
; ALL: RET 0, implicit %xmm0
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>), %2(<4 x s32>), %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
|
||||
%xmm0 = COPY %1(<4 x s32>)
|
||||
@ -45,26 +46,26 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_unmerge_v256
|
||||
# ALL-LABEL: name: test_unmerge_v256
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %1 = COPY %0.sub_ymm
|
||||
# ALL-NEXT: %2 = VEXTRACTF64x4Zrr %0, 1
|
||||
# ALL-NEXT: %ymm0 = COPY %1
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
|
||||
; ALL-LABEL: name: test_unmerge_v256
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: vr512
|
||||
; ALL-NEXT: id: 1, class: vr256x
|
||||
; ALL-NEXT: id: 2, class: vr256x
|
||||
; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_ymm
|
||||
; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]] = VEXTRACTF64x4Zrr [[DEF]], 1
|
||||
; ALL: %ymm0 = COPY [[COPY]]
|
||||
; ALL: RET 0, implicit %ymm0
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<8 x s32>), %2(<8 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
|
||||
%ymm0 = COPY %1(<8 x s32>)
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
@ -24,14 +25,9 @@
|
||||
...
|
||||
---
|
||||
name: test_xor_i8
|
||||
# ALL-LABEL: name: test_xor_i8
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -40,15 +36,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %dil
|
||||
# ALL-NEXT: %1 = COPY %sil
|
||||
# ALL-NEXT: %2 = XOR8rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %al = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %al
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_xor_i8
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr8
|
||||
; ALL-NEXT: id: 1, class: gr8
|
||||
; ALL-NEXT: id: 2, class: gr8
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %dil
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %sil
|
||||
; ALL: [[XOR8rr:%[0-9]+]] = XOR8rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %al = COPY [[XOR8rr]]
|
||||
; ALL: RET 0, implicit %al
|
||||
%0(s8) = COPY %dil
|
||||
%1(s8) = COPY %sil
|
||||
%2(s8) = G_XOR %0, %1
|
||||
@ -58,14 +59,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_xor_i16
|
||||
# ALL-LABEL: name: test_xor_i16
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -74,15 +70,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %di
|
||||
# ALL-NEXT: %1 = COPY %si
|
||||
# ALL-NEXT: %2 = XOR16rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %ax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_xor_i16
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr16
|
||||
; ALL-NEXT: id: 1, class: gr16
|
||||
; ALL-NEXT: id: 2, class: gr16
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %di
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %si
|
||||
; ALL: [[XOR16rr:%[0-9]+]] = XOR16rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %ax = COPY [[XOR16rr]]
|
||||
; ALL: RET 0, implicit %ax
|
||||
%0(s16) = COPY %di
|
||||
%1(s16) = COPY %si
|
||||
%2(s16) = G_XOR %0, %1
|
||||
@ -92,14 +93,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_xor_i32
|
||||
# ALL-LABEL: name: test_xor_i32
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -108,15 +104,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %edi
|
||||
# ALL-NEXT: %1 = COPY %esi
|
||||
# ALL-NEXT: %2 = XOR32rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %eax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %eax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %edi, %esi
|
||||
|
||||
; ALL-LABEL: name: test_xor_i32
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr32
|
||||
; ALL-NEXT: id: 1, class: gr32
|
||||
; ALL-NEXT: id: 2, class: gr32
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %edi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %esi
|
||||
; ALL: [[XOR32rr:%[0-9]+]] = XOR32rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %eax = COPY [[XOR32rr]]
|
||||
; ALL: RET 0, implicit %eax
|
||||
%0(s32) = COPY %edi
|
||||
%1(s32) = COPY %esi
|
||||
%2(s32) = G_XOR %0, %1
|
||||
@ -126,14 +127,9 @@ body: |
|
||||
...
|
||||
---
|
||||
name: test_xor_i64
|
||||
# ALL-LABEL: name: test_xor_i64
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: gpr, preferred-register: '' }
|
||||
- { id: 1, class: gpr, preferred-register: '' }
|
||||
@ -142,15 +138,20 @@ liveins:
|
||||
fixedStack:
|
||||
stack:
|
||||
constants:
|
||||
# ALL: %0 = COPY %rdi
|
||||
# ALL-NEXT: %1 = COPY %rsi
|
||||
# ALL-NEXT: %2 = XOR64rr %0, %1, implicit-def %eflags
|
||||
# ALL-NEXT: %rax = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %rax
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %rdi, %rsi
|
||||
|
||||
; ALL-LABEL: name: test_xor_i64
|
||||
; ALL: registers:
|
||||
; ALL-NEXT: id: 0, class: gr64
|
||||
; ALL-NEXT: id: 1, class: gr64
|
||||
; ALL-NEXT: id: 2, class: gr64
|
||||
; ALL: [[COPY:%[0-9]+]] = COPY %rdi
|
||||
; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
|
||||
; ALL: [[XOR64rr:%[0-9]+]] = XOR64rr [[COPY]], [[COPY1]], implicit-def %eflags
|
||||
; ALL: %rax = COPY [[XOR64rr]]
|
||||
; ALL: RET 0, implicit %rax
|
||||
%0(s64) = COPY %rdi
|
||||
%1(s64) = COPY %rsi
|
||||
%2(s64) = G_XOR %0, %1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user