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[ARM] Add 'fillValidCPUArchList' to ARM targets

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This is a support change for a CFE change (https://reviews.llvm.org/D42978)
that allows march and -target-cpu to list the valid targets in a note. The changes
are limited to the ARM/AArch64, since this is the only target that gets the CPU
list from LLVM.

llvm-svn: 324623
This commit is contained in:
Erich Keane 2018-02-08 16:48:54 +00:00
parent 8de40b8f47
commit 588c8b4c0e
3 changed files with 44 additions and 0 deletions
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2
include/llvm/Support/TargetParser.h
View File

@ -137,6 +137,7 @@ unsigned parseFPU(StringRef FPU);
ArchKind parseArch(StringRef Arch);
unsigned parseArchExt(StringRef ArchExt);
ArchKind parseCPUArch(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
ISAKind parseArchISA(StringRef Arch);
EndianKind parseArchEndian(StringRef Arch);
ProfileKind parseArchProfile(StringRef Arch);
@ -205,6 +206,7 @@ unsigned parseFPU(StringRef FPU);
AArch64::ArchKind parseArch(StringRef Arch);
ArchExtKind parseArchExt(StringRef ArchExt);
ArchKind parseCPUArch(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
ARM::ISAKind parseArchISA(StringRef Arch);
ARM::EndianKind parseArchEndian(StringRef Arch);
ARM::ProfileKind parseArchProfile(StringRef Arch);

14
lib/Support/TargetParser.cpp
View File

@ -689,6 +689,20 @@ ARM::ArchKind llvm::ARM::parseCPUArch(StringRef CPU) {
return ARM::ArchKind::INVALID;
}
void llvm::ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
for (const CpuNames<ARM::ArchKind> &Arch : CPUNames) {
if (Arch.ArchID != ARM::ArchKind::INVALID)
Values.push_back(Arch.getName());
}
}
void llvm::AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
for (const CpuNames<AArch64::ArchKind> &Arch : AArch64CPUNames) {
if (Arch.ArchID != AArch64::ArchKind::INVALID)
Values.push_back(Arch.getName());
}
}
// ARM, Thumb, AArch64
ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
return StringSwitch<ARM::ISAKind>(Arch)

28
unittests/Support/TargetParserTest.cpp
View File

@ -279,6 +279,20 @@ TEST(TargetParserTest, testARMCPU) {
"7-S"));
}
static constexpr int NumARMCPUArchs = 82;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;
ARM::fillValidCPUArchList(List);
// No list exists for these in this test suite, so ensure all are
// valid, and match the expected 'magic' count.
EXPECT_EQ(List.size(), NumARMCPUArchs);
for(StringRef CPU : List) {
EXPECT_NE(ARM::parseCPUArch(CPU), ARM::ArchKind::INVALID);
}
}
TEST(TargetParserTest, testInvalidARMArch) {
auto InvalidArchStrings = {"armv", "armv99", "noarm"};
for (const char* InvalidArch : InvalidArchStrings)
@ -747,6 +761,20 @@ TEST(TargetParserTest, testAArch64CPU) {
"8-A"));
}
static constexpr int NumAArch64CPUArchs = 19;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
AArch64::fillValidCPUArchList(List);
// No list exists for these in this test suite, so ensure all are
// valid, and match the expected 'magic' count.
EXPECT_EQ(List.size(), NumAArch64CPUArchs);
for(StringRef CPU : List) {
EXPECT_NE(AArch64::parseCPUArch(CPU), AArch64::ArchKind::INVALID);
}
}
bool testAArch64Arch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
unsigned ArchAttr) {
AArch64::ArchKind AK = AArch64::parseArch(Arch);