RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

add vector_shuffle

Browse Source 
llvm-svn: 26891
This commit is contained in:
Chris Lattner 2006-03-20 05:40:45 +00:00
parent eb65663732
commit 5892479894
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/TargetSelectionDAG.td
View File

@ -51,6 +51,15 @@ class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
int BigOperandNum = BigOp; int BigOperandNum = BigOp;
} }
/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
/// packed vector types, and that ThisOp is the result of
/// MVT::getIntVectorWithNumElements with the number of elements that ThisOp
/// has.
class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
: SDTypeConstraint<ThisOp> {
int OtherOpNum = OtherOp;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Selection DAG Type Profile definitions. // Selection DAG Type Profile definitions.
// //
@ -161,6 +170,10 @@ def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore
SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>; ]>;
def SDTVecShuffle : SDTypeProfile<1, 3, [
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Selection DAG Node Properties. // Selection DAG Node Properties.
// //
@ -293,6 +306,9 @@ def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
def extld : SDNode<"ISD::EXTLOAD" , SDTExtLoad, [SDNPHasChain]>; def extld : SDNode<"ISD::EXTLOAD" , SDTExtLoad, [SDNPHasChain]>;
def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Selection DAG Condition Codes // Selection DAG Condition Codes