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[RISCV][NFC] Add explicit type i64 to RV64 only patterns.

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Add explicit type i64 to RV64 only patterns to stop emitting unneeded i32 patterns.

It can reduce the isel table size.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100089
This commit is contained in:
Jim Lin 2021-04-09 09:36:33 +08:00
parent a8234cdb0e
commit 58e3420193
1 changed files with 10 additions and 10 deletions
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20
lib/Target/RISCV/RISCVInstrInfoA.td
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@ -334,15 +334,15 @@ defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D">;
/// 64-bit AMOs
def : Pat<(atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr)),
(AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
def : Pat<(atomic_load_sub_64_acquire GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_sub_64_acquire GPR:$addr, GPR:$incr)),
(AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
def : Pat<(atomic_load_sub_64_release GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_sub_64_release GPR:$addr, GPR:$incr)),
(AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
def : Pat<(atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr)),
(AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
def : Pat<(atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr)),
(AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
/// 64-bit pseudo AMOs
@ -350,15 +350,15 @@ def : Pat<(atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr),
def PseudoAtomicLoadNand64 : PseudoAMO;
// Ordering constants must be kept in sync with the AtomicOrdering enum in
// AtomicOrdering.h.
def : Pat<(atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>;
def : Pat<(atomic_load_nand_64_acquire GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_nand_64_acquire GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>;
def : Pat<(atomic_load_nand_64_release GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_nand_64_release GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>;
def : Pat<(atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>;
def : Pat<(atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr),
def : Pat<(i64 (atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i64,