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https://github.com/RPCS3/llvm-mirror.git
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[X86] Add masked MCVTSI2P/MCVTUI2P ISD opcodes to model the cvtqq2ps cvtuqq2ps nodes that produce less than 128-bits of results.
These nodes zero the upper half of the result and can't be represented with vselect. llvm-svn: 351666
This commit is contained in:
Craig Topper
parent
62e6ab67bb
commit
59062585b0
@ -22118,7 +22118,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getMergeValues(Results, dl);
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}
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case CVTPD2PS_MASK:
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case CVTPD2I_MASK:
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case CVTPD2DQ_MASK:
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case CVTQQ2PS_MASK:
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case TRUNCATE_TO_REG: {
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SDValue Src = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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@ -27464,6 +27465,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CVTTS2UI_RND: return "X86ISD::CVTTS2UI_RND";
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case X86ISD::CVTSI2P: return "X86ISD::CVTSI2P";
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case X86ISD::CVTUI2P: return "X86ISD::CVTUI2P";
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case X86ISD::MCVTSI2P: return "X86ISD::MCVTSI2P";
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case X86ISD::MCVTUI2P: return "X86ISD::MCVTUI2P";
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case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
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case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
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case X86ISD::MULTISHIFT: return "X86ISD::MULTISHIFT";
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@ -515,6 +515,7 @@ namespace llvm {
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// Masked versions of above. Used for v2f64->v4f32.
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// SRC, PASSTHRU, MASK
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MCVTP2SI, MCVTP2UI, MCVTTP2SI, MCVTTP2UI,
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MCVTSI2P, MCVTUI2P,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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@ -8383,8 +8383,7 @@ multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// Convert Signed/Unsigned Quardword to Float
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multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SDNode OpNode128, SDNode OpNodeRnd,
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X86SchedWriteWidths sched> {
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SDNode OpNodeRnd, X86SchedWriteWidths sched> {
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let Predicates = [HasDQI] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode,
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sched.ZMM>,
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@ -8396,9 +8395,9 @@ multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// memory forms of these instructions in Asm Parcer. They have the same
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// due to the same reason.
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode128,
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sched.XMM, "{1to2}", "{x}">, EVEX_V128,
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NotEVEX2VEXConvertible;
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, null_frag,
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sched.XMM, "{1to2}", "{x}", i128mem, VK2WM>,
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EVEX_V128, NotEVEX2VEXConvertible;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
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sched.YMM, "{1to4}", "{y}">, EVEX_V256,
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NotEVEX2VEXConvertible;
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@ -8501,11 +8500,11 @@ defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
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X86VUintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS,
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EVEX_CD8<64, CD8VF>;
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defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP,
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defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
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X86VSintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, PS,
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EVEX_CD8<64, CD8VF>;
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defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP,
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defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
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X86VUintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, XD,
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EVEX_CD8<64, CD8VF>;
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@ -8815,6 +8814,64 @@ let Predicates = [HasDQI, HasVLX] in {
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def : Pat<(X86vzmovl (v2f64 (bitconvert
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(v4f32 (X86VUintToFP (v2i64 VR128X:$src)))))),
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(VCVTUQQ2PSZ128rr VR128X:$src)>;
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// Special patterns to allow use of X86VMSintToFP for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4f32 (X86VSintToFP (v2i64 VR128X:$src))),
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(VCVTQQ2PSZ128rr VR128X:$src)>;
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def : Pat<(X86VMSintToFP (v2i64 VR128X:$src), (v4f32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTQQ2PSZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86VMSintToFP (v2i64 VR128X:$src), v4f32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTQQ2PSZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(v4f32 (X86VSintToFP (loadv2i64 addr:$src))),
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(VCVTQQ2PSZ128rm addr:$src)>;
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def : Pat<(X86VMSintToFP (loadv2i64 addr:$src), (v4f32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTQQ2PSZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86VMSintToFP (loadv2i64 addr:$src), v4f32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTQQ2PSZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4f32 (X86VSintToFP (v2i64 (X86VBroadcast (loadi64 addr:$src))))),
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(VCVTQQ2PSZ128rmb addr:$src)>;
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def : Pat<(X86VMSintToFP (v2i64 (X86VBroadcast (loadi64 addr:$src))),
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(v4f32 VR128X:$src0), VK2WM:$mask),
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(VCVTQQ2PSZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86VMSintToFP (v2i64 (X86VBroadcast (loadi64 addr:$src))),
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v4f32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTQQ2PSZ128rmbkz VK2WM:$mask, addr:$src)>;
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// Special patterns to allow use of X86VMUintToFP for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4f32 (X86VUintToFP (v2i64 VR128X:$src))),
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(VCVTUQQ2PSZ128rr VR128X:$src)>;
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def : Pat<(X86VMUintToFP (v2i64 VR128X:$src), (v4f32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTUQQ2PSZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86VMUintToFP (v2i64 VR128X:$src), v4f32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTUQQ2PSZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(v4f32 (X86VUintToFP (loadv2i64 addr:$src))),
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(VCVTUQQ2PSZ128rm addr:$src)>;
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def : Pat<(X86VMUintToFP (loadv2i64 addr:$src), (v4f32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTUQQ2PSZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86VMUintToFP (loadv2i64 addr:$src), v4f32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTUQQ2PSZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4f32 (X86VUintToFP (v2i64 (X86VBroadcast (loadi64 addr:$src))))),
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(VCVTUQQ2PSZ128rmb addr:$src)>;
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def : Pat<(X86VMUintToFP (v2i64 (X86VBroadcast (loadi64 addr:$src))),
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(v4f32 VR128X:$src0), VK2WM:$mask),
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(VCVTUQQ2PSZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86VMUintToFP (v2i64 (X86VBroadcast (loadi64 addr:$src))),
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v4f32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTUQQ2PSZ128rmbkz VK2WM:$mask, addr:$src)>;
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}
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let Predicates = [HasDQI, NoVLX] in {
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@ -597,6 +597,13 @@ def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>;
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def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>;
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// Masked versions of above
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def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<0>, SDTCisInt<1>,
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SDTCisSameSizeAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>;
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def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCisFP<1>,
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SDTCisSameSizeAs<0, 1>,
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@ -604,6 +611,9 @@ def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>;
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def X86VMSintToFP : SDNode<"X86ISD::MCVTSI2P", SDTMVintToFP>;
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def X86VMUintToFP : SDNode<"X86ISD::MCVTUI2P", SDTMVintToFP>;
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def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>;
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def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>;
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def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
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@ -30,7 +30,7 @@ enum IntrinsicType : uint16_t {
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IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK,
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INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK,
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COMPRESS_EXPAND_IN_REG,
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TRUNCATE_TO_REG, CVTPS2PH_MASK, CVTPD2I_MASK,
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TRUNCATE_TO_REG, CVTPS2PH_MASK, CVTPD2DQ_MASK, CVTQQ2PS_MASK,
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TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32,
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FIXUPIMM, FIXUPIMM_MASKZ, FIXUPIMMS,
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FIXUPIMMS_MASKZ, GATHER_AVX2,
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@ -509,7 +509,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CONFLICT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_512, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND), //er
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, CVTPD2I_MASK,
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, CVTPD2DQ_MASK,
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X86ISD::CVTP2SI, X86ISD::MCVTP2SI),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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@ -523,7 +523,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_128, CVTPD2I_MASK,
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_128, CVTPD2DQ_MASK,
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X86ISD::CVTP2UI, X86ISD::MCVTP2UI),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_256, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2UI, 0),
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@ -563,8 +563,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTP2UI, X86ISD::CVTP2UI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtqq2pd_512, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTSI2P, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_128, CVTQQ2PS_MASK,
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X86ISD::CVTSI2P, X86ISD::MCVTSI2P),
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X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_256, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_512, INTR_TYPE_1OP_MASK,
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@ -573,7 +573,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::VFPROUNDS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtss2sd_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::VFPEXTS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, CVTPD2I_MASK,
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, CVTPD2DQ_MASK,
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X86ISD::CVTTP2SI, X86ISD::MCVTTP2SI),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2SI, X86ISD::CVTTP2SI_RND),
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@ -583,7 +583,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2SI, X86ISD::CVTTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, CVTPD2I_MASK,
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, CVTPD2DQ_MASK,
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X86ISD::CVTTP2UI, X86ISD::MCVTTP2UI),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_256, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2UI, 0),
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@ -619,8 +619,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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ISD::UINT_TO_FP, X86ISD::UINT_TO_FP_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtuqq2pd_512, INTR_TYPE_1OP_MASK,
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ISD::UINT_TO_FP, X86ISD::UINT_TO_FP_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTUI2P, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_128, CVTQQ2PS_MASK,
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X86ISD::CVTUI2P, X86ISD::MCVTUI2P),
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X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_256, INTR_TYPE_1OP_MASK,
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ISD::UINT_TO_FP, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_512, INTR_TYPE_1OP_MASK,
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