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llvm-svn: 130942
This commit is contained in:
Andrew Trick 2011-05-05 19:24:06 +00:00
parent ab39b8319b
commit 5946376390
1 changed files with 16 additions and 16 deletions
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32
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -120,7 +120,7 @@ static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
// such aliases. // such aliases.
if (PSV->isAliased(MFI)) if (PSV->isAliased(MFI))
return 0; return 0;
MayAlias = PSV->mayAlias(MFI); MayAlias = PSV->mayAlias(MFI);
return V; return V;
} }
@ -174,7 +174,7 @@ void ScheduleDAGInstrs::AddSchedBarrierDeps() {
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
SE = BB->succ_end(); SI != SE; ++SI) SE = BB->succ_end(); SI != SE; ++SI)
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
E = (*SI)->livein_end(); I != E; ++I) { E = (*SI)->livein_end(); I != E; ++I) {
unsigned Reg = *I; unsigned Reg = *I;
if (Seen.insert(Reg)) if (Seen.insert(Reg))
Uses[Reg].push_back(&ExitSU); Uses[Reg].push_back(&ExitSU);
@ -411,11 +411,11 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
#define STORE_LOAD_LATENCY 1 #define STORE_LOAD_LATENCY 1
unsigned TrueMemOrderLatency = 0; unsigned TrueMemOrderLatency = 0;
if (TID.isCall() || MI->hasUnmodeledSideEffects() || if (TID.isCall() || MI->hasUnmodeledSideEffects() ||
(MI->hasVolatileMemoryRef() && (MI->hasVolatileMemoryRef() &&
(!TID.mayLoad() || !MI->isInvariantLoad(AA)))) { (!TID.mayLoad() || !MI->isInvariantLoad(AA)))) {
// Be conservative with these and add dependencies on all memory // Be conservative with these and add dependencies on all memory
// references, even those that are known to not alias. // references, even those that are known to not alias.
for (std::map<const Value *, SUnit *>::iterator I = for (std::map<const Value *, SUnit *>::iterator I =
NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) { NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
} }
@ -458,9 +458,9 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
// A store to a specific PseudoSourceValue. Add precise dependencies. // A store to a specific PseudoSourceValue. Add precise dependencies.
// Record the def in MemDefs, first adding a dep if there is // Record the def in MemDefs, first adding a dep if there is
// an existing def. // an existing def.
std::map<const Value *, SUnit *>::iterator I = std::map<const Value *, SUnit *>::iterator I =
((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
std::map<const Value *, SUnit *>::iterator IE = std::map<const Value *, SUnit *>::iterator IE =
((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
if (I != IE) { if (I != IE) {
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0, I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
@ -513,37 +513,37 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
if (MI->isInvariantLoad(AA)) { if (MI->isInvariantLoad(AA)) {
// Invariant load, no chain dependencies needed! // Invariant load, no chain dependencies needed!
} else { } else {
if (const Value *V = if (const Value *V =
getUnderlyingObjectForInstr(MI, MFI, MayAlias)) { getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
// A load from a specific PseudoSourceValue. Add precise dependencies. // A load from a specific PseudoSourceValue. Add precise dependencies.
std::map<const Value *, SUnit *>::iterator I = std::map<const Value *, SUnit *>::iterator I =
((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
std::map<const Value *, SUnit *>::iterator IE = std::map<const Value *, SUnit *>::iterator IE =
((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
if (I != IE) if (I != IE)
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0, I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
/*isNormalMemory=*/true)); /*isNormalMemory=*/true));
if (MayAlias) if (MayAlias)
AliasMemUses[V].push_back(SU); AliasMemUses[V].push_back(SU);
else else
NonAliasMemUses[V].push_back(SU); NonAliasMemUses[V].push_back(SU);
} else { } else {
// A load with no underlying object. Depend on all // A load with no underlying object. Depend on all
// potentially aliasing stores. // potentially aliasing stores.
for (std::map<const Value *, SUnit *>::iterator I = for (std::map<const Value *, SUnit *>::iterator I =
AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
PendingLoads.push_back(SU); PendingLoads.push_back(SU);
MayAlias = true; MayAlias = true;
} }
// Add dependencies on alias and barrier chains, if needed. // Add dependencies on alias and barrier chains, if needed.
if (MayAlias && AliasChain) if (MayAlias && AliasChain)
AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
if (BarrierChain) if (BarrierChain)
BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
} }
} }
} }
@ -572,11 +572,11 @@ void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
} }
} }
void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use, void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
SDep& dep) const { SDep& dep) const {
if (!InstrItins || InstrItins->isEmpty()) if (!InstrItins || InstrItins->isEmpty())
return; return;
// For a data dependency with a known register... // For a data dependency with a known register...
if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0)) if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
return; return;