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Improvements to MIPS64 assembler:
- Teach it about dadd[i] instructions and move pseudo-instruction - Make it parse the register names correctly (for N32 / N64) llvm-svn: 165506
This commit is contained in:
David Chisnall
parent
54aac8803f
commit
59a1cfd847
@ -415,48 +415,82 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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int MipsAsmParser::matchRegisterName(StringRef Name) {
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int CC = StringSwitch<unsigned>(Name)
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.Case("zero", Mips::ZERO)
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.Case("a0", Mips::A0)
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.Case("a1", Mips::A1)
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.Case("a2", Mips::A2)
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.Case("a3", Mips::A3)
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.Case("v0", Mips::V0)
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.Case("v1", Mips::V1)
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.Case("s0", Mips::S0)
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.Case("s1", Mips::S1)
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.Case("s2", Mips::S2)
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.Case("s3", Mips::S3)
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.Case("s4", Mips::S4)
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.Case("s5", Mips::S5)
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.Case("s6", Mips::S6)
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.Case("s7", Mips::S7)
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.Case("k0", Mips::K0)
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.Case("k1", Mips::K1)
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.Case("sp", Mips::SP)
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.Case("fp", Mips::FP)
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.Case("gp", Mips::GP)
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.Case("ra", Mips::RA)
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.Case("t0", Mips::T0)
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.Case("t1", Mips::T1)
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.Case("t2", Mips::T2)
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.Case("t3", Mips::T3)
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.Case("t4", Mips::T4)
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.Case("t5", Mips::T5)
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.Case("t6", Mips::T6)
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.Case("t7", Mips::T7)
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.Case("t8", Mips::T8)
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.Case("t9", Mips::T9)
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.Case("at", Mips::AT)
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.Case("fcc0", Mips::FCC0)
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.Default(-1);
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int CC;
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if (!isMips64())
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CC = StringSwitch<unsigned>(Name)
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.Case("zero", Mips::ZERO)
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.Case("a0", Mips::A0)
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.Case("a1", Mips::A1)
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.Case("a2", Mips::A2)
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.Case("a3", Mips::A3)
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.Case("v0", Mips::V0)
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.Case("v1", Mips::V1)
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.Case("s0", Mips::S0)
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.Case("s1", Mips::S1)
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.Case("s2", Mips::S2)
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.Case("s3", Mips::S3)
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.Case("s4", Mips::S4)
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.Case("s5", Mips::S5)
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.Case("s6", Mips::S6)
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.Case("s7", Mips::S7)
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.Case("k0", Mips::K0)
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.Case("k1", Mips::K1)
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.Case("sp", Mips::SP)
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.Case("fp", Mips::FP)
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.Case("gp", Mips::GP)
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.Case("ra", Mips::RA)
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.Case("t0", Mips::T0)
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.Case("t1", Mips::T1)
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.Case("t2", Mips::T2)
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.Case("t3", Mips::T3)
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.Case("t4", Mips::T4)
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.Case("t5", Mips::T5)
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.Case("t6", Mips::T6)
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.Case("t7", Mips::T7)
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.Case("t8", Mips::T8)
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.Case("t9", Mips::T9)
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.Case("at", Mips::AT)
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.Case("fcc0", Mips::FCC0)
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.Default(-1);
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else
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CC = StringSwitch<unsigned>(Name)
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.Case("zero", Mips::ZERO_64)
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.Case("at", Mips::AT_64)
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.Case("v0", Mips::V0_64)
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.Case("v1", Mips::V1_64)
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.Case("a0", Mips::A0_64)
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.Case("a1", Mips::A1_64)
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.Case("a2", Mips::A2_64)
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.Case("a3", Mips::A3_64)
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.Case("a4", Mips::T0_64)
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.Case("a5", Mips::T1_64)
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.Case("a6", Mips::T2_64)
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.Case("a7", Mips::T3_64)
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.Case("t4", Mips::T4_64)
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.Case("t5", Mips::T5_64)
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.Case("t6", Mips::T6_64)
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.Case("t7", Mips::T7_64)
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.Case("s0", Mips::S0_64)
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.Case("s1", Mips::S1_64)
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.Case("s2", Mips::S2_64)
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.Case("s3", Mips::S3_64)
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.Case("s4", Mips::S4_64)
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.Case("s5", Mips::S5_64)
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.Case("s6", Mips::S6_64)
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.Case("s7", Mips::S7_64)
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.Case("t8", Mips::T8_64)
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.Case("t9", Mips::T9_64)
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.Case("kt0", Mips::K0_64)
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.Case("kt1", Mips::K1_64)
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.Case("gp", Mips::GP_64)
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.Case("sp", Mips::SP_64)
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.Case("fp", Mips::FP_64)
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.Case("s8", Mips::FP_64)
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.Case("ra", Mips::RA_64)
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.Default(-1);
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if (CC != -1) {
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// 64 bit register in Mips are following 32 bit definitions.
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if (isMips64())
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CC++;
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if (CC != -1)
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return CC;
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}
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if (Name[0] == 'f') {
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StringRef NumString = Name.substr(1);
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@ -544,7 +578,8 @@ int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic) {
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if (RegNum > 31)
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return -1;
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return getReg(Mips::CPURegsRegClassID, RegNum);
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// MIPS64 registers are numbered 1 after the 32-bit equivalents
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return getReg(Mips::CPURegsRegClassID, RegNum) + isMips64();
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}
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int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
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@ -83,6 +83,8 @@ let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding],
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16,
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CPU64Regs>;
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def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
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CPU64Regs>;
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def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
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@ -93,6 +95,7 @@ def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
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def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithOverflowR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>;
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def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
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def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
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def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
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@ -307,3 +310,8 @@ def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
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// bswap MipsPattern
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def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
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