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https://github.com/RPCS3/llvm-mirror.git
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Reduce the number of arguments in the instruction builder and make some
improvements on instruction selection that account for register and frame index bases. Patch contributed by Jeff Cohen. Thanks Jeff! llvm-svn: 16110
This commit is contained in:
Reid Spencer
parent
dac3230f2c
commit
59cb27bcdc
@ -237,23 +237,21 @@ namespace {
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/// getAddressingMode - Get the addressing mode to use to address the
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/// specified value. The returned value should be used with addFullAddress.
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void getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
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unsigned &IndexReg, unsigned &Disp);
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void getAddressingMode(Value *Addr, X86AddressMode &AM);
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/// getGEPIndex - This is used to fold GEP instructions into X86 addressing
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/// expressions.
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void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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std::vector<Value*> &GEPOps,
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std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
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unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
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std::vector<const Type*> &GEPTypes,
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X86AddressMode &AM);
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/// isGEPFoldable - Return true if the specified GEP can be completely
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/// folded into the addressing mode of a load/store or lea instruction.
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bool isGEPFoldable(MachineBasicBlock *MBB,
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Value *Src, User::op_iterator IdxBegin,
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User::op_iterator IdxEnd, unsigned &BaseReg,
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unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
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User::op_iterator IdxEnd, X86AddressMode &AM);
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/// emitGEPOperation - Common code shared between visitGetElementPtrInst and
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/// constant expression GEP support.
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@ -812,23 +810,28 @@ void ISel::InsertFPRegKills() {
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}
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void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
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unsigned &IndexReg, unsigned &Disp) {
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BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
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void ISel::getAddressingMode(Value *Addr, X86AddressMode &AM) {
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = 0; AM.Scale = 1; AM.IndexReg = 0; AM.Disp = 0;
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if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
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if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
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BaseReg, Scale, IndexReg, Disp))
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AM))
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return;
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} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
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if (CE->getOpcode() == Instruction::GetElementPtr)
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if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
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BaseReg, Scale, IndexReg, Disp))
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AM))
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return;
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} else if (AllocaInst *AI = dyn_castFixedAlloca(Addr)) {
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AM.BaseType = X86AddressMode::FrameIndexBase;
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AM.Base.FrameIndex = getFixedSizedAllocaFI(AI);
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return;
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}
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// If it's not foldable, reset addr mode.
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BaseReg = getReg(Addr);
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Scale = 1; IndexReg = 0; Disp = 0;
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = getReg(Addr);
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AM.Scale = 1; AM.IndexReg = 0; AM.Disp = 0;
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}
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// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
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@ -1995,12 +1998,10 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), AM);
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addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), AM);
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}
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return;
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}
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@ -2020,12 +2021,10 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), AM);
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addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), AM);
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}
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return;
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}
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@ -2352,8 +2351,13 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
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case 5:
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case 9:
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if (Class == cInt) {
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addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, DestReg),
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op0Reg, ConstRHS-1, op0Reg, 0);
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X86AddressMode AM;
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = op0Reg;
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AM.Scale = ConstRHS-1;
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AM.IndexReg = op0Reg;
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AM.Disp = 0;
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addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, DestReg), AM);
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return;
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}
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case -3:
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@ -2361,8 +2365,13 @@ void ISel::doMultiplyConst(MachineBasicBlock *MBB,
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case -9:
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if (Class == cInt) {
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TmpReg = makeAnotherReg(DestTy);
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addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TmpReg),
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op0Reg, -ConstRHS-1, op0Reg, 0);
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X86AddressMode AM;
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = op0Reg;
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AM.Scale = -ConstRHS-1;
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AM.IndexReg = op0Reg;
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AM.Disp = 0;
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addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TmpReg), AM);
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BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(TmpReg);
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return;
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}
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@ -2444,12 +2453,10 @@ void ISel::visitMul(BinaryOperator &I) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(LI->getOperand(0), AM);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), AM);
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}
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return;
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}
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@ -2588,12 +2595,10 @@ void ISel::visitDivRem(BinaryOperator &I) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg,
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Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(LI->getOperand(0), AM);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), AM);
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}
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return;
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}
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@ -2609,10 +2614,9 @@ void ISel::visitDivRem(BinaryOperator &I) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), FI);
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} else {
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unsigned BaseReg, Scale, IndexReg, Disp;
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getAddressingMode(LI->getOperand(0), BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r),
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BaseReg, Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(LI->getOperand(0), AM);
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addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), AM);
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}
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return;
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}
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@ -2938,10 +2942,9 @@ void ISel::visitLoadInst(LoadInst &I) {
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unsigned FI = getFixedSizedAllocaFI(AI);
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addFrameReference(BuildMI(BB, Opcode[Class], 4, DestReg), FI);
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} else {
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unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
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getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode[Class], 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(I.getOperand(0), AM);
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addFullAddress(BuildMI(BB, Opcode[Class], 4, DestReg), AM);
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}
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return;
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} else {
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@ -3011,17 +3014,15 @@ void ISel::visitLoadInst(LoadInst &I) {
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addFrameReference(BuildMI(BB, Opcode, 4, DestReg), FI);
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}
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} else {
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unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
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getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(I.getOperand(0), AM);
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if (Class == cLong) {
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
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BaseReg, Scale, IndexReg, Disp+4);
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg), AM);
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AM.Disp += 4;
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addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), AM);
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} else {
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addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
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BaseReg, Scale, IndexReg, Disp);
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addFullAddress(BuildMI(BB, Opcode, 4, DestReg), AM);
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}
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}
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}
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@ -3030,13 +3031,8 @@ void ISel::visitLoadInst(LoadInst &I) {
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/// instruction.
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///
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void ISel::visitStoreInst(StoreInst &I) {
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unsigned BaseReg = ~0U, Scale = ~0U, IndexReg = ~0U, Disp = ~0U;
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unsigned AllocaFrameIdx = ~0U;
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if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(1)))
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AllocaFrameIdx = getFixedSizedAllocaFI(AI);
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else
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getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
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X86AddressMode AM;
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getAddressingMode(I.getOperand(1), AM);
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const Type *ValTy = I.getOperand(0)->getType();
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unsigned Class = getClassB(ValTy);
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@ -3044,42 +3040,20 @@ void ISel::visitStoreInst(StoreInst &I) {
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
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uint64_t Val = CI->getRawValue();
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if (Class == cLong) {
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if (AllocaFrameIdx != ~0U) {
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx).addImm(Val & ~0U);
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx, 4).addImm(Val>>32);
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} else {
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
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}
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(Val & ~0U);
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AM.Disp += 4;
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(Val>>32);
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} else {
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static const unsigned Opcodes[] = {
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X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
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};
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unsigned Opcode = Opcodes[Class];
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addImm(Val);
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else
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addFullAddress(BuildMI(BB, Opcode, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(Val);
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addFullAddress(BuildMI(BB, Opcode, 5), AM).addImm(Val);
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}
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} else if (isa<ConstantPointerNull>(I.getOperand(0))) {
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5), AllocaFrameIdx).addImm(0);
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else
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(0);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(0);
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} else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
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AllocaFrameIdx).addImm(CB->getValue());
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else
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addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
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addFullAddress(BuildMI(BB, X86::MOV8mi, 5), AM).addImm(CB->getValue());
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} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) {
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// Store constant FP values with integer instructions to avoid having to
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// load the constants from the constant pool then do a store.
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@ -3089,45 +3063,24 @@ void ISel::visitStoreInst(StoreInst &I) {
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float F;
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} V;
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V.F = CFP->getValue();
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx).addImm(V.I);
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else
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm(V.I);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(V.I);
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} else {
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union {
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uint64_t I;
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double F;
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} V;
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V.F = CFP->getValue();
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if (AllocaFrameIdx != ~0U) {
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx).addImm((unsigned)V.I);
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addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
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AllocaFrameIdx, 4).addImm(unsigned(V.I >> 32));
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} else {
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp).addImm((unsigned)V.I);
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
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BaseReg, Scale, IndexReg, Disp+4).addImm(
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm((unsigned)V.I);
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AM.Disp += 4;
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addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(
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unsigned(V.I >> 32));
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}
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}
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} else if (Class == cLong) {
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unsigned ValReg = getReg(I.getOperand(0));
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if (AllocaFrameIdx != ~0U) {
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addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
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AllocaFrameIdx).addReg(ValReg);
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addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
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AllocaFrameIdx, 4).addReg(ValReg+1);
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} else {
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addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
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BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
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addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
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BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
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}
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addFullAddress(BuildMI(BB, X86::MOV32mr, 5), AM).addReg(ValReg);
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AM.Disp += 4;
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addFullAddress(BuildMI(BB, X86::MOV32mr, 5), AM).addReg(ValReg+1);
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} else {
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unsigned ValReg = getReg(I.getOperand(0));
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static const unsigned Opcodes[] = {
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@ -3136,11 +3089,7 @@ void ISel::visitStoreInst(StoreInst &I) {
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unsigned Opcode = Opcodes[Class];
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if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
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if (AllocaFrameIdx != ~0U)
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addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addReg(ValReg);
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else
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addFullAddress(BuildMI(BB, Opcode, 1+4),
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BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
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addFullAddress(BuildMI(BB, Opcode, 1+4), AM).addReg(ValReg);
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}
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}
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@ -3539,8 +3488,8 @@ void ISel::visitVAArgInst(VAArgInst &I) {
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void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
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// If this GEP instruction will be folded into all of its users, we don't need
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// to explicitly calculate it!
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unsigned A, B, C, D;
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if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
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X86AddressMode AM;
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if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), AM)) {
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// Check all of the users of the instruction to see if they are loads and
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// stores.
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bool AllWillFold = true;
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@ -3575,15 +3524,16 @@ void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
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///
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void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
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std::vector<Value*> &GEPOps,
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std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
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unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
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std::vector<const Type*> &GEPTypes,
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X86AddressMode &AM) {
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const TargetData &TD = TM.getTargetData();
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// Clear out the state we are working with...
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BaseReg = 0; // No base register
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Scale = 1; // Unit scale
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IndexReg = 0; // No index register
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Disp = 0; // No displacement
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AM.BaseType = X86AddressMode::RegBase;
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AM.Base.Reg = 0; // No base register
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AM.Scale = 1; // Unit scale
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AM.IndexReg = 0; // No index register
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AM.Disp = 0; // No displacement
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|
||||
// While there are GEP indexes that can be folded into the current address,
|
||||
// keep processing them.
|
||||
@ -3597,7 +3547,7 @@ void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
|
||||
// structure is in memory. Since the structure index must be constant, we
|
||||
// can get its value and use it to find the right byte offset from the
|
||||
// StructLayout class's list of structure member offsets.
|
||||
Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
|
||||
AM.Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
|
||||
GEPOps.pop_back(); // Consume a GEP operand
|
||||
GEPTypes.pop_back();
|
||||
} else {
|
||||
@ -3612,18 +3562,18 @@ void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
|
||||
// If idx is a constant, fold it into the offset.
|
||||
unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
|
||||
if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
|
||||
Disp += TypeSize*CSI->getValue();
|
||||
AM.Disp += TypeSize*CSI->getValue();
|
||||
} else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
|
||||
Disp += TypeSize*CUI->getValue();
|
||||
AM.Disp += TypeSize*CUI->getValue();
|
||||
} else {
|
||||
// If the index reg is already taken, we can't handle this index.
|
||||
if (IndexReg) return;
|
||||
if (AM.IndexReg) return;
|
||||
|
||||
// If this is a size that we can handle, then add the index as
|
||||
switch (TypeSize) {
|
||||
case 1: case 2: case 4: case 8:
|
||||
// These are all acceptable scales on X86.
|
||||
Scale = TypeSize;
|
||||
AM.Scale = TypeSize;
|
||||
break;
|
||||
default:
|
||||
// Otherwise, we can't handle this scale
|
||||
@ -3635,7 +3585,7 @@ void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
|
||||
CI->getOperand(0)->getType() == Type::UIntTy)
|
||||
idx = CI->getOperand(0);
|
||||
|
||||
IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
|
||||
AM.IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
|
||||
}
|
||||
|
||||
GEPOps.pop_back(); // Consume a GEP operand
|
||||
@ -3646,22 +3596,23 @@ void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
|
||||
// GEPTypes is empty, which means we have a single operand left. Set it as
|
||||
// the base register.
|
||||
//
|
||||
assert(BaseReg == 0);
|
||||
assert(AM.Base.Reg == 0);
|
||||
|
||||
#if 0 // FIXME: TODO!
|
||||
if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
|
||||
// FIXME: When we can add FrameIndex values as the first operand, we can
|
||||
// make GEP's of allocas MUCH more efficient!
|
||||
unsigned FI = getFixedSizedAllocaFI(AI);
|
||||
if (AllocaInst *AI = dyn_castFixedAlloca(GEPOps.back())) {
|
||||
AM.BaseType = X86AddressMode::FrameIndexBase;
|
||||
AM.Base.FrameIndex = getFixedSizedAllocaFI(AI);
|
||||
GEPOps.pop_back();
|
||||
return;
|
||||
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
|
||||
}
|
||||
|
||||
#if 0 // FIXME: TODO!
|
||||
if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
|
||||
// FIXME: When addressing modes are more powerful/correct, we could load
|
||||
// global addresses directly as 32-bit immediates.
|
||||
}
|
||||
#endif
|
||||
|
||||
BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
|
||||
AM.Base.Reg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
|
||||
GEPOps.pop_back(); // Consume the last GEP operand
|
||||
}
|
||||
|
||||
@ -3670,8 +3621,7 @@ void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
|
||||
/// folded into the addressing mode of a load/store or lea instruction.
|
||||
bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
|
||||
Value *Src, User::op_iterator IdxBegin,
|
||||
User::op_iterator IdxEnd, unsigned &BaseReg,
|
||||
unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
|
||||
User::op_iterator IdxEnd, X86AddressMode &AM) {
|
||||
|
||||
std::vector<Value*> GEPOps;
|
||||
GEPOps.resize(IdxEnd-IdxBegin+1);
|
||||
@ -3684,7 +3634,7 @@ bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
|
||||
|
||||
MachineBasicBlock::iterator IP;
|
||||
if (MBB) IP = MBB->end();
|
||||
getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
|
||||
getGEPIndex(MBB, IP, GEPOps, GEPTypes, AM);
|
||||
|
||||
// We can fold it away iff the getGEPIndex call eliminated all operands.
|
||||
return GEPOps.empty();
|
||||
@ -3723,23 +3673,23 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
||||
// Keep emitting instructions until we consume the entire GEP instruction.
|
||||
while (!GEPOps.empty()) {
|
||||
unsigned OldSize = GEPOps.size();
|
||||
unsigned BaseReg, Scale, IndexReg, Disp;
|
||||
getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
|
||||
X86AddressMode AM;
|
||||
getGEPIndex(MBB, IP, GEPOps, GEPTypes, AM);
|
||||
|
||||
if (GEPOps.size() != OldSize) {
|
||||
// getGEPIndex consumed some of the input. Build an LEA instruction here.
|
||||
unsigned NextTarget = 0;
|
||||
if (!GEPOps.empty()) {
|
||||
assert(BaseReg == 0 &&
|
||||
assert(AM.Base.Reg == 0 &&
|
||||
"getGEPIndex should have left the base register open for chaining!");
|
||||
NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
|
||||
NextTarget = AM.Base.Reg = makeAnotherReg(Type::UIntTy);
|
||||
}
|
||||
|
||||
if (IndexReg == 0 && Disp == 0)
|
||||
BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
|
||||
if (AM.BaseType == X86AddressMode::RegBase &&
|
||||
AM.IndexReg == 0 && AM.Disp == 0)
|
||||
BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(AM.Base.Reg);
|
||||
else
|
||||
addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg),
|
||||
BaseReg, Scale, IndexReg, Disp);
|
||||
addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg), AM);
|
||||
--IP;
|
||||
TargetReg = NextTarget;
|
||||
} else if (GEPTypes.empty()) {
|
||||
|
||||
@ -28,6 +28,29 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// X86AddressMode - This struct holds a generalized full x86 address mode.
|
||||
/// The base register can be a frame index, which will eventually be replaced
|
||||
/// with BP or SP and Disp being offsetted accordingly.
|
||||
/// FIXME: add support for globals as a new base type.
|
||||
struct X86AddressMode {
|
||||
enum {
|
||||
UnknownBase,
|
||||
RegBase,
|
||||
FrameIndexBase
|
||||
} BaseType;
|
||||
|
||||
union {
|
||||
unsigned Reg;
|
||||
int FrameIndex;
|
||||
} Base;
|
||||
|
||||
unsigned Scale;
|
||||
unsigned IndexReg;
|
||||
unsigned Disp;
|
||||
|
||||
X86AddressMode() : BaseType(UnknownBase) {}
|
||||
};
|
||||
|
||||
/// addDirectMem - This function is used to add a direct memory reference to the
|
||||
/// current instruction -- that is, a dereference of an address in a register,
|
||||
/// with no scale, index or displacement. An example is: DWORD PTR [EAX].
|
||||
@ -50,12 +73,16 @@ inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
|
||||
}
|
||||
|
||||
inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
|
||||
unsigned BaseReg,
|
||||
unsigned Scale,
|
||||
unsigned IndexReg,
|
||||
unsigned Disp) {
|
||||
assert (Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
|
||||
return MIB.addReg(BaseReg).addZImm(Scale).addReg(IndexReg).addSImm(Disp);
|
||||
const X86AddressMode &AM) {
|
||||
assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
|
||||
|
||||
if (AM.BaseType == X86AddressMode::RegBase)
|
||||
MIB.addReg(AM.Base.Reg);
|
||||
else if (AM.BaseType == X86AddressMode::FrameIndexBase)
|
||||
MIB.addFrameIndex(AM.Base.FrameIndex);
|
||||
else
|
||||
assert (0);
|
||||
return MIB.addZImm(AM.Scale).addReg(AM.IndexReg).addSImm(AM.Disp);
|
||||
}
|
||||
|
||||
/// addFrameReference - This function is used to add a reference to the base of
|
||||
|
||||
Loading…
Reference in New Issue
Block a user