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[AArch64][SVE] Move TableGen class definitions for gather loads (NFC)

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Move 2 intrinsic class definitions so that they're all clustered in
one place.

Patch submitted to test commit access.
This commit is contained in:
Andrzej Warzynski 2019-12-11 08:58:01 +00:00
parent b9f3a80ecc
commit 5a023bc2ff
1 changed files with 17 additions and 17 deletions
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34
include/llvm/IR/IntrinsicsAArch64.td
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@ -959,15 +959,6 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
llvm_i32_ty],
[IntrNoMem]>;
class AdvSIMD_GatherLoad_64bitOffset_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i64_ty>
],
[IntrReadMem, IntrArgMemOnly]>;
class SVE2_3VectorArg_Long_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
@ -987,14 +978,6 @@ class AdvSIMD_GatherLoad_64bitOffset_Intrinsic
// to reuse currently identical class definitions.
class AdvSIMD_SVE_LOGB_Intrinsic : AdvSIMD_SVE_CNT_Intrinsic;
class AdvSIMD_GatherLoad_32bitOffset_Intrinsic
: Intrinsic<[ llvm_anyvector_ty ],
[
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>, llvm_anyvector_ty
],
[ IntrReadMem, IntrArgMemOnly ]>;
// This class of intrinsics are not intended to be useful within LLVM IR but
// are instead here to support some of the more regid parts of the ACLE.
class Builtin_SVCVT<string name, LLVMType OUT, LLVMType IN>
@ -1024,6 +1007,23 @@ class AdvSIMD_SVE_WHILE_Intrinsic
[llvm_anyint_ty, LLVMMatchType<1>],
[IntrNoMem]>;
class AdvSIMD_GatherLoad_64bitOffset_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i64_ty>
],
[IntrReadMem, IntrArgMemOnly]>;
class AdvSIMD_GatherLoad_32bitOffset_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>, llvm_anyvector_ty
],
[IntrReadMem, IntrArgMemOnly]>;
class AdvSIMD_GatherLoad_VecTorBase_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[