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Added tmp instructions to preserve ssa.
llvm-svn: 19632
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51590b615c
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@ -626,9 +626,13 @@ CreateSETUWConst(uint32_t C,
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int32_t sC = (int32_t) C;
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int32_t sC = (int32_t) C;
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bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
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bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
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//Create TmpInstruction for intermediate values
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TmpInstruction *tmpReg;
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// Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
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// Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
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if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
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if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
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miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
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tmpReg = new TmpInstruction(mcfi, PointerType::get(val->getType()), (Instruction*) val);
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miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(tmpReg);
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miSETHI->getOperand(0).markHi32();
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miSETHI->getOperand(0).markHi32();
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mvec.push_back(miSETHI);
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mvec.push_back(miSETHI);
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}
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}
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@ -638,7 +642,7 @@ CreateSETUWConst(uint32_t C,
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if (miSETHI==NULL || C & MAXLO) {
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if (miSETHI==NULL || C & MAXLO) {
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if (miSETHI) {
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if (miSETHI) {
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// unsigned value with high-order bits set using SETHI
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// unsigned value with high-order bits set using SETHI
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miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest);
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miOR = BuildMI(V9::ORi,3).addReg(tmpReg).addZImm(C).addRegDef(dest);
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miOR->getOperand(1).markLo32();
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miOR->getOperand(1).markLo32();
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} else {
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} else {
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// unsigned or small signed value that fits in simm13 field of OR
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// unsigned or small signed value that fits in simm13 field of OR
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@ -648,6 +652,8 @@ CreateSETUWConst(uint32_t C,
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}
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}
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mvec.push_back(miOR);
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mvec.push_back(miOR);
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}
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}
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else
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mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg).addMReg(SparcV9::g0).addRegDef(dest));
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assert((miSETHI || miOR) && "Oops, no code was generated!");
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assert((miSETHI || miOR) && "Oops, no code was generated!");
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}
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}
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@ -662,13 +668,19 @@ static inline void
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CreateSETSWConst(int32_t C,
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CreateSETSWConst(int32_t C,
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Instruction* dest, std::vector<MachineInstr*>& mvec,
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Instruction* dest, std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi, Value* val) {
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MachineCodeForInstruction& mcfi, Value* val) {
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//TmpInstruction for intermediate values
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TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val);
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// Set the low 32 bits of dest
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// Set the low 32 bits of dest
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CreateSETUWConst((uint32_t) C, dest, mvec, mcfi, val, /*isSigned*/true);
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CreateSETUWConst((uint32_t) C, tmpReg, mvec, mcfi, val, /*isSigned*/true);
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// Sign-extend to the high 32 bits if needed.
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// Sign-extend to the high 32 bits if needed.
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// NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
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// NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
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if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
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if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
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mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
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mvec.push_back(BuildMI(V9::SRAi5,3).addReg(tmpReg).addZImm(0).addRegDef(dest));
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else
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mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg).addMReg(SparcV9::g0).addRegDef(dest));
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}
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}
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/// CreateSETXConst - Set a 64-bit signed or unsigned constant in the
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/// CreateSETXConst - Set a 64-bit signed or unsigned constant in the
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@ -689,15 +701,21 @@ CreateSETXConst(uint64_t C,
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// Code to set the upper 32 bits of the value in register `tmpReg'
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// Code to set the upper 32 bits of the value in register `tmpReg'
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CreateSETUWConst((C >> 32), tmpReg, mvec, mcfi, val);
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CreateSETUWConst((C >> 32), tmpReg, mvec, mcfi, val);
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//TmpInstruction for intermediate values
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TmpInstruction *tmpReg2 = new TmpInstruction(mcfi, (Instruction*) val);
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// Shift tmpReg left by 32 bits
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// Shift tmpReg left by 32 bits
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mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
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mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
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.addRegDef(tmpReg));
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.addRegDef(tmpReg2));
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//TmpInstruction for intermediate values
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TmpInstruction *tmpReg3 = new TmpInstruction(mcfi, (Instruction*) val);
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// Code to set the low 32 bits of the value in register `dest'
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// Code to set the low 32 bits of the value in register `dest'
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CreateSETUWConst(C, dest, mvec, mcfi, val);
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CreateSETUWConst(C, tmpReg3, mvec, mcfi, val);
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// dest = OR(tmpReg, dest)
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// dest = OR(tmpReg, dest)
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mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
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mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg3).addReg(tmpReg2).addRegDef(dest));
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}
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}
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/// CreateSETUWLabel - Set a 32-bit constant (given by a symbolic label) in
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/// CreateSETUWLabel - Set a 32-bit constant (given by a symbolic label) in
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