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[X86][SSE] Combine (VSRLI (VSRAI X, Y), (NumSignBits-1)) -> (VSRLI X, (NumSignBits-1))
Part 3 of 3. Differential Revision: https://reviews.llvm.org/D31347 llvm-svn: 298782
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@ -31075,13 +31075,14 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
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bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;
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EVT VT = N->getValueType(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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unsigned NumBitsPerElt = VT.getScalarSizeInBits();
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assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 &&
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"Unexpected value type");
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// Out of range logical bit shifts are guaranteed to be zero.
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// Out of range arithmetic bit shifts splat the sign bit.
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APInt ShiftVal = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
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APInt ShiftVal = cast<ConstantSDNode>(N1)->getAPIntValue();
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if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt)) {
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if (LogicalShift)
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return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N));
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@ -31097,6 +31098,13 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
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if (ISD::isBuildVectorAllZeros(N0.getNode()))
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return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N));
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// fold (VSRLI (VSRAI X, Y), 31) -> (VSRLI X, 31).
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// This VSRLI only looks at the sign bit, which is unmodified by VSRAI.
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// TODO - support other sra opcodes as needed.
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if (Opcode == X86ISD::VSRLI && (ShiftVal + 1) == NumBitsPerElt &&
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N0.getOpcode() == X86ISD::VSRAI)
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return DAG.getNode(X86ISD::VSRLI, SDLoc(N), VT, N0.getOperand(0), N1);
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// We can decode 'whole byte' logical bit shifts as shuffles.
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if (LogicalShift && (ShiftVal.getZExtValue() % 8) == 0) {
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SDValue Op(N, 0);
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@ -253,7 +253,6 @@ define <4 x i32> @and_or_zext_v4i16(<4 x i16> %a0) {
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define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) {
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; CHECK-LABEL: ashr_mask1_v8i16:
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; CHECK: # BB#0:
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; CHECK-NEXT: psraw $15, %xmm0
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; CHECK-NEXT: psrlw $15, %xmm0
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; CHECK-NEXT: retq
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%1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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