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[GlobalISel][AArch64] Select G_FFLOOR
This teaches the legalizer about G_FFLOOR, and lets us select G_FFLOOR in AArch64. It updates the existing floating point tests, and adds a select-floor.mir test. Differential Revision: https://reviews.llvm.org/D57486 llvm-svn: 353722
This commit is contained in:
Jessica Paquette
parent
6d08ea2404
commit
5a40815c0d
@ -1358,6 +1358,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_FREM:
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case TargetOpcode::G_FCEIL:
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case TargetOpcode::G_FFLOOR:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FSIN:
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case TargetOpcode::G_FLOG10:
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@ -2147,6 +2148,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
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case G_FLOG2:
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case G_FLOG10:
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case G_FCEIL:
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case G_FFLOOR:
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case G_INTRINSIC_ROUND:
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case G_INTRINSIC_TRUNC:
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case G_FCOS:
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@ -126,7 +126,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
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getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT})
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getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR})
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// If we don't have full FP16 support, then scalarize the elements of
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// vectors containing fp16 types.
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.fewerElementsIf(
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@ -392,6 +392,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
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case TargetOpcode::G_FPEXT:
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case TargetOpcode::G_FPTRUNC:
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case TargetOpcode::G_FCEIL:
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case TargetOpcode::G_FFLOOR:
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case TargetOpcode::G_FNEG:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FSIN:
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130
test/CodeGen/AArch64/GlobalISel/select-floor.mir
Normal file
130
test/CodeGen/AArch64/GlobalISel/select-floor.mir
Normal file
@ -0,0 +1,130 @@
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# RUN: llc -verify-machineinstrs -mtriple aarch64--- \
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# RUN: -run-pass=instruction-select -mattr=+fullfp16 -global-isel %s -o - \
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# RUN: | FileCheck %s
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...
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---
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name: floor_float
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_float
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; CHECK: %{{[0-9]+}}:fpr32 = FRINTMSr %{{[0-9]+}}
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liveins: $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_FFLOOR %0
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$s0 = COPY %1(s32)
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...
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---
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name: floor_double
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_double
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; CHECK: %{{[0-9]+}}:fpr64 = FRINTMDr %{{[0-9]+}}
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liveins: $d0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = G_FFLOOR %0
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$d0 = COPY %1(s64)
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...
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---
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name: floor_v2f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_v2f32
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; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv2f32 %{{[0-9]+}}
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liveins: $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_FFLOOR %0
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$d0 = COPY %1(<2 x s32>)
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...
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---
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name: floor_v4f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_v4f32
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; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv4f32 %{{[0-9]+}}
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liveins: $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_FFLOOR %0
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$q0 = COPY %1(<4 x s32>)
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...
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---
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name: floor_v2f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_v2f64
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; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv2f64 %{{[0-9]+}}
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liveins: $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_FFLOOR %0
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$q0 = COPY %1(<2 x s64>)
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...
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---
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name: floor_v4f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_v4f16
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; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv4f16 %{{[0-9]+}}
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liveins: $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_FFLOOR %0
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$d0 = COPY %1(<4 x s16>)
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...
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---
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name: floor_v8f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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body: |
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bb.0:
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; CHECK-LABEL: name: floor_v8f16
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; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv8f16 %{{[0-9]+}}
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liveins: $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_FFLOOR %0
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$q0 = COPY %1(<8 x s16>)
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...
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@ -141,12 +141,20 @@ define %v4f16 @test_v4f16.fabs(%v4f16 %a) {
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%1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v4f16.floor
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define %v4f16 @test_v4f16.floor(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.floor:
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; CHECK-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}}
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: frintm.4h
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; CHECK-FP16-NEXT: ret
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; GISEL-LABEL: test_v4f16.floor:
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; GISEL-NOFP16-COUNT-4: frintm s{{[0-9]+}}, s{{[0-9]+}}
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; GISEL-FP16-NOT: fcvt
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; GISEL-FP16: frintm.4h
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; GISEL-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.floor.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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@ -342,12 +350,20 @@ define %v8f16 @test_v8f16.fabs(%v8f16 %a) {
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%1 = call %v8f16 @llvm.fabs.v8f16(%v8f16 %a)
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ret %v8f16 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v8f16.floor
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define %v8f16 @test_v8f16.floor(%v8f16 %a) {
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; CHECK-LABEL: test_v8f16.floor:
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; CHECK-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}}
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: frintm.8h
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; CHECK-FP16-NEXT: ret
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; GISEL-LABEL: test_v8f16.floor:
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; GISEL-NOFP16-COUNT-8: frintm s{{[0-9]+}}, s{{[0-9]+}}
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; GISEL-FP16-NOT: fcvt
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; GISEL-FP16: frintm.8h
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; GISEL-FP16-NEXT: ret
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%1 = call %v8f16 @llvm.floor.v8f16(%v8f16 %a)
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ret %v8f16 %1
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}
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@ -516,9 +532,13 @@ define %v2f32 @test_v2f32.fabs(%v2f32 %a) {
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%1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v2f32.floor
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; CHECK-LABEL: test_v2f32.floor:
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; GISEL-LABEL: test_v2f32.floor:
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define %v2f32 @test_v2f32.floor(%v2f32 %a) {
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; CHECK: frintm.2s
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; GISEL: frintm.2s
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%1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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@ -671,9 +691,13 @@ define %v4f32 @test_v4f32.fabs(%v4f32 %a) {
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%1 = call %v4f32 @llvm.fabs.v4f32(%v4f32 %a)
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ret %v4f32 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v4f32.floor
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; CHECK: test_v4f32.floor:
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; GISEL: test_v4f32.floor:
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define %v4f32 @test_v4f32.floor(%v4f32 %a) {
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; CHECK: frintm.4s
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; GISEL frintm.4s
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%1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a)
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ret %v4f32 %1
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}
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@ -826,9 +850,13 @@ define %v2f64 @test_v2f64.fabs(%v2f64 %a) {
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%1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
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ret %v2f64 %1
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}
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; FALLBACK-NOT: remark{{.*}}test_v2f64.floor
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; CHECK: test_v2f64.floor:
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; GISEL: test_v2f64.floor:
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define %v2f64 @test_v2f64.floor(%v2f64 %a) {
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; CHECK: frintm.2d
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; GISEL: frintm.2d
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%1 = call %v2f64 @llvm.floor.v2f64(%v2f64 %a)
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ret %v2f64 %1
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}
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@ -1168,6 +1168,19 @@ define float @test_copysign_extended(half %a, half %b) #0 {
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; CHECK-FP16-NEXT: frintm h0, h0
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; CHECK-FP16-NEXT: ret
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; FALLBACK-NOT: remark:{{.*}}test_floor
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; FALLBACK-FP16-NOT: remark:{{.*}}test_floor
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; GISEL-CVT-LABEL: test_floor:
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; GISEL-CVT-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
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; GISEL-CVT-NEXT: frintm [[INT32:s[0-9]+]], [[FLOAT32]]
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; GISEL-CVT-NEXT: fcvt h0, [[INT32]]
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; GISEL-CVT-NEXT: ret
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; GISEL-FP16-LABEL: test_floor:
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; GISEL-FP16-NEXT: frintm h0, h0
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; GISEL-FP16-NEXT: ret
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define half @test_floor(half %a) #0 {
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%r = call half @llvm.floor.f16(half %a)
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ret half %r
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