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[AMDGPU, NFC] Refactor FP/BP spill index code in emitPrologue/emitEpilogue

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Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D98617
This commit is contained in:
RamNalamothu 2021-03-16 16:36:24 +05:30
parent 533dfa60d2
commit 5a521663a1
1 changed files with 36 additions and 55 deletions
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91
lib/Target/AMDGPU/SIFrameLowering.cpp
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@ -838,6 +838,13 @@ static Register buildScratchExecCopy(LivePhysRegs &LiveRegs,
return ScratchExecCopy;
}
// A StackID of SGPRSpill implies that this is a spill from SGPR to VGPR.
// Otherwise we are spilling to memory.
static bool spilledToMemory(const MachineFunction &MF, int SaveIndex) {
const MachineFrameInfo &MFI = MF.getFrameInfo();
return MFI.getStackID(SaveIndex) != TargetStackID::SGPRSpill;
}
void SIFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
@ -869,23 +876,8 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
// turn on all lanes before doing the spill to memory.
Register ScratchExecCopy;
bool HasFPSaveIndex = FuncInfo->FramePointerSaveIndex.hasValue();
bool SpillFPToMemory = false;
// A StackID of SGPRSpill implies that this is a spill from SGPR to VGPR.
// Otherwise we are spilling the FP to memory.
if (HasFPSaveIndex) {
SpillFPToMemory = MFI.getStackID(*FuncInfo->FramePointerSaveIndex) !=
TargetStackID::SGPRSpill;
}
bool HasBPSaveIndex = FuncInfo->BasePointerSaveIndex.hasValue();
bool SpillBPToMemory = false;
// A StackID of SGPRSpill implies that this is a spill from SGPR to VGPR.
// Otherwise we are spilling the BP to memory.
if (HasBPSaveIndex) {
SpillBPToMemory = MFI.getStackID(*FuncInfo->BasePointerSaveIndex) !=
TargetStackID::SGPRSpill;
}
Optional<int> FPSaveIndex = FuncInfo->FramePointerSaveIndex;
Optional<int> BPSaveIndex = FuncInfo->BasePointerSaveIndex;
for (const SIMachineFunctionInfo::SGPRSpillVGPRCSR &Reg
: FuncInfo->getSGPRSpillVGPRs()) {
@ -901,8 +893,9 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
Reg.FI.getValue());
}
if (HasFPSaveIndex && SpillFPToMemory) {
assert(!MFI.isDeadObjectIndex(FuncInfo->FramePointerSaveIndex.getValue()));
if (FPSaveIndex && spilledToMemory(MF, *FPSaveIndex)) {
const int FramePtrFI = *FPSaveIndex;
assert(!MFI.isDeadObjectIndex(FramePtrFI));
if (!ScratchExecCopy)
ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true);
@ -916,12 +909,12 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
.addReg(FramePtrReg);
buildPrologSpill(ST, LiveRegs, MBB, MBBI, TII, TmpVGPR,
FuncInfo->getScratchRSrcReg(), StackPtrReg,
FuncInfo->FramePointerSaveIndex.getValue());
FuncInfo->getScratchRSrcReg(), StackPtrReg, FramePtrFI);
}
if (HasBPSaveIndex && SpillBPToMemory) {
assert(!MFI.isDeadObjectIndex(*FuncInfo->BasePointerSaveIndex));
if (BPSaveIndex && spilledToMemory(MF, *BPSaveIndex)) {
const int BasePtrFI = *BPSaveIndex;
assert(!MFI.isDeadObjectIndex(BasePtrFI));
if (!ScratchExecCopy)
ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true);
@ -935,8 +928,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
.addReg(BasePtrReg);
buildPrologSpill(ST, LiveRegs, MBB, MBBI, TII, TmpVGPR,
FuncInfo->getScratchRSrcReg(), StackPtrReg,
*FuncInfo->BasePointerSaveIndex);
FuncInfo->getScratchRSrcReg(), StackPtrReg, BasePtrFI);
}
if (ScratchExecCopy) {
@ -949,13 +941,13 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
}
// In this case, spill the FP to a reserved VGPR.
if (HasFPSaveIndex && !SpillFPToMemory) {
const int FI = FuncInfo->FramePointerSaveIndex.getValue();
assert(!MFI.isDeadObjectIndex(FI));
if (FPSaveIndex && !spilledToMemory(MF, *FPSaveIndex)) {
const int FramePtrFI = *FPSaveIndex;
assert(!MFI.isDeadObjectIndex(FramePtrFI));
assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
assert(MFI.getStackID(FramePtrFI) == TargetStackID::SGPRSpill);
ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill =
FuncInfo->getSGPRToVGPRSpills(FI);
FuncInfo->getSGPRToVGPRSpills(FramePtrFI);
assert(Spill.size() == 1);
// Save FP before setting it up.
@ -967,8 +959,8 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF,
}
// In this case, spill the BP to a reserved VGPR.
if (HasBPSaveIndex && !SpillBPToMemory) {
const int BasePtrFI = *FuncInfo->BasePointerSaveIndex;
if (BPSaveIndex && !spilledToMemory(MF, *BPSaveIndex)) {
const int BasePtrFI = *BPSaveIndex;
assert(!MFI.isDeadObjectIndex(BasePtrFI));
assert(MFI.getStackID(BasePtrFI) == TargetStackID::SGPRSpill);
@ -1107,19 +1099,8 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
const Register BasePtrReg =
TRI.hasBasePointer(MF) ? TRI.getBaseRegister() : Register();
bool HasFPSaveIndex = FuncInfo->FramePointerSaveIndex.hasValue();
bool SpillFPToMemory = false;
if (HasFPSaveIndex) {
SpillFPToMemory = MFI.getStackID(*FuncInfo->FramePointerSaveIndex) !=
TargetStackID::SGPRSpill;
}
bool HasBPSaveIndex = FuncInfo->BasePointerSaveIndex.hasValue();
bool SpillBPToMemory = false;
if (HasBPSaveIndex) {
SpillBPToMemory = MFI.getStackID(*FuncInfo->BasePointerSaveIndex) !=
TargetStackID::SGPRSpill;
}
Optional<int> FPSaveIndex = FuncInfo->FramePointerSaveIndex;
Optional<int> BPSaveIndex = FuncInfo->BasePointerSaveIndex;
if (RoundedSize != 0 && hasFP(MF)) {
BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)
@ -1141,10 +1122,10 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
}
Register ScratchExecCopy;
if (HasFPSaveIndex) {
const int FI = FuncInfo->FramePointerSaveIndex.getValue();
assert(!MFI.isDeadObjectIndex(FI));
if (SpillFPToMemory) {
if (FPSaveIndex) {
const int FramePtrFI = *FPSaveIndex;
assert(!MFI.isDeadObjectIndex(FramePtrFI));
if (spilledToMemory(MF, FramePtrFI)) {
if (!ScratchExecCopy)
ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false);
@ -1153,14 +1134,14 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
if (!TempVGPR)
report_fatal_error("failed to find free scratch register");
buildEpilogReload(ST, LiveRegs, MBB, MBBI, TII, TempVGPR,
FuncInfo->getScratchRSrcReg(), StackPtrReg, FI);
FuncInfo->getScratchRSrcReg(), StackPtrReg, FramePtrFI);
BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), FramePtrReg)
.addReg(TempVGPR, RegState::Kill);
} else {
// Reload from VGPR spill.
assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
assert(MFI.getStackID(FramePtrFI) == TargetStackID::SGPRSpill);
ArrayRef<SIMachineFunctionInfo::SpilledReg> Spill =
FuncInfo->getSGPRToVGPRSpills(FI);
FuncInfo->getSGPRToVGPRSpills(FramePtrFI);
assert(Spill.size() == 1);
BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READLANE_B32), FramePtrReg)
.addReg(Spill[0].VGPR)
@ -1168,10 +1149,10 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF,
}
}
if (HasBPSaveIndex) {
const int BasePtrFI = *FuncInfo->BasePointerSaveIndex;
if (BPSaveIndex) {
const int BasePtrFI = *BPSaveIndex;
assert(!MFI.isDeadObjectIndex(BasePtrFI));
if (SpillBPToMemory) {
if (spilledToMemory(MF, BasePtrFI)) {
if (!ScratchExecCopy)
ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false);