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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures.
There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". llvm-svn: 276013
This commit is contained in:
Tim Northover
parent
3e610ad27b
commit
5a799be389
@ -295,7 +295,8 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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FeatureV7Clrex]>;
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FeatureV7Clrex]>;
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def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
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def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
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"Support ARM v8 instructions",
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"Support ARM v8 instructions",
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[HasV7Ops, FeatureAcquireRelease]>;
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[HasV7Ops, FeatureAcquireRelease,
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FeatureT2XtPk]>;
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
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"Support ARM v8.1a instructions",
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"Support ARM v8.1a instructions",
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[HasV8Ops]>;
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[HasV8Ops]>;
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@ -388,7 +389,8 @@ def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
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def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
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def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
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def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
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def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
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FeatureDSP]>;
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FeatureDSP,
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FeatureT2XtPk]>;
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def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
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def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
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@ -409,13 +411,15 @@ def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
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FeatureNEON,
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FeatureNEON,
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FeatureDB,
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FeatureDB,
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FeatureDSP,
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FeatureDSP,
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FeatureAClass]>;
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FeatureAClass,
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FeatureT2XtPk]>;
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def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
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def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
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FeatureDB,
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FeatureDB,
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FeatureDSP,
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FeatureDSP,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureRClass]>;
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FeatureRClass,
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FeatureT2XtPk]>;
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def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
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def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
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FeatureThumb2,
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FeatureThumb2,
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@ -570,7 +574,6 @@ def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
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FeatureSlowFPBrcc,
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FeatureSlowFPBrcc,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding,
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FeatureT2XtPk,
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FeatureMP,
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FeatureMP,
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FeatureVFP4]>;
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FeatureVFP4]>;
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@ -581,7 +584,6 @@ def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
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FeatureHasVMLxHazards,
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FeatureHasVMLxHazards,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding,
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FeatureT2XtPk,
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FeatureMP,
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FeatureMP,
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FeatureVFP4,
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FeatureVFP4,
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FeatureHWDiv,
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FeatureHWDiv,
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@ -595,15 +597,13 @@ def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
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FeatureSlowFPBrcc,
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FeatureSlowFPBrcc,
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FeatureHasVMLxHazards,
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FeatureHasVMLxHazards,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding]>;
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FeatureT2XtPk]>;
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def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
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def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureTrustZone,
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FeatureHasVMLxHazards,
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FeatureHasVMLxHazards,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding,
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FeatureT2XtPk,
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FeatureFP16,
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FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR,
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FeatureExpandMLx,
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FeatureExpandMLx,
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@ -618,7 +618,6 @@ def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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FeatureTrustZone,
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FeatureTrustZone,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding,
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FeatureT2XtPk,
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FeatureVFP4,
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FeatureVFP4,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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@ -632,7 +631,6 @@ def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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FeatureMuxedUnits,
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FeatureMuxedUnits,
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FeatureTrustZone,
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FeatureTrustZone,
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FeatureT2XtPk,
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FeatureVFP4,
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FeatureVFP4,
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FeatureMP,
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FeatureMP,
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FeatureCheckVLDnAlign,
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FeatureCheckVLDnAlign,
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@ -647,7 +645,6 @@ def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
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FeatureTrustZone,
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FeatureTrustZone,
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FeatureMP,
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FeatureMP,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding,
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FeatureT2XtPk,
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FeatureVFP4,
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FeatureVFP4,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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@ -662,7 +659,6 @@ def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
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FeatureMuxedUnits,
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FeatureMuxedUnits,
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FeatureCheckVLDnAlign,
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FeatureCheckVLDnAlign,
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FeatureVMLxForwarding,
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FeatureVMLxForwarding,
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FeatureT2XtPk,
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FeatureFP16,
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FeatureFP16,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR,
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FeatureVFP4,
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FeatureVFP4,
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@ -672,7 +668,6 @@ def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
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def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
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def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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FeatureNEONForFP,
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FeatureNEONForFP,
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FeatureT2XtPk,
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FeatureVFP4,
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FeatureVFP4,
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FeatureMP,
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FeatureMP,
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FeatureHWDiv,
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FeatureHWDiv,
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@ -691,8 +686,7 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
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// FIXME: R4 has currently the same ProcessorModel as A8.
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// FIXME: R4 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
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def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR]>;
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FeatureT2XtPk]>;
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// FIXME: R4F has currently the same ProcessorModel as A8.
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// FIXME: R4F has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
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def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
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@ -701,8 +695,7 @@ def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureVFP3,
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FeatureVFP3,
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FeatureD16,
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FeatureD16,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR]>;
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FeatureT2XtPk]>;
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// FIXME: R5 has currently the same ProcessorModel as A8.
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// FIXME: R5 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
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def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
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@ -712,8 +705,7 @@ def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
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FeatureSlowFPBrcc,
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FeatureSlowFPBrcc,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR]>;
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FeatureT2XtPk]>;
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// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
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// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
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def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
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def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
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@ -725,8 +717,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
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FeatureSlowFPBrcc,
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FeatureSlowFPBrcc,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR]>;
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FeatureT2XtPk]>;
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def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
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def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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@ -737,8 +728,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
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FeatureSlowFPBrcc,
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FeatureSlowFPBrcc,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureHasSlowFPVMLx,
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FeatureAvoidPartialCPSR,
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FeatureAvoidPartialCPSR]>;
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FeatureT2XtPk]>;
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def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
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def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
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def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
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def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
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@ -755,42 +745,36 @@ def : ProcNoItin<"cortex-m7", [ARMv7em,
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def : ProcNoItin<"cortex-a32", [ARMv8a,
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def : ProcNoItin<"cortex-a32", [ARMv8a,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
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def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
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def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
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def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
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def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
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def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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@ -798,7 +782,6 @@ def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
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def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
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def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
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FeatureHasRetAddrStack,
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FeatureHasRetAddrStack,
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FeatureNEONForFP,
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FeatureNEONForFP,
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FeatureT2XtPk,
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FeatureVFP4,
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FeatureVFP4,
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FeatureMP,
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FeatureMP,
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FeatureHWDiv,
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FeatureHWDiv,
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@ -812,7 +795,6 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
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def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
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def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
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FeatureHWDiv,
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FeatureHWDiv,
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FeatureHWDivARM,
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FeatureHWDivARM,
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FeatureT2XtPk,
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FeatureCrypto,
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FeatureCrypto,
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FeatureCRC]>;
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FeatureCRC]>;
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17
test/MC/ARM/pkhbt-archs.s
Normal file
17
test/MC/ARM/pkhbt-archs.s
Normal file
@ -0,0 +1,17 @@
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@ RUN: llvm-mc -triple thumbv7 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
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@ RUN: llvm-mc -triple thumbv8 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
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@ RUN: llvm-mc -triple thumbv7em %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
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@ RUN: llvm-mc -triple thumbv6t2 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
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@ RUN: not llvm-mc -triple thumbv6 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
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@ RUN: not llvm-mc -triple thumbv7m %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
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@ RUN: not llvm-mc -triple thumbv8m.main %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
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@ RUN: not llvm-mc -triple thumbv8m.base %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
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@ Instruction is "v6T2, v7" in ARMARM-AR, "v7em" in ARMARM-M. So it's
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@ valid on everything v6t2 upwards, except v7m. Also apparently not on
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@ v8m (going by present behaviour).
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pkhbt r1, r2, r3, lsl #24
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@ CHECK-VALID: pkhbt r1, r2, r3, lsl #24 @ encoding: [0xc2,0xea,0x03,0x61]
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@ CHECK-INVALID: error:
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