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misched prep: Comment the ScheduleDAGInstrs interface.

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llvm-svn: 152259
This commit is contained in:
Andrew Trick 2012-03-07 23:00:59 +00:00
parent df0a76e646
commit 5ab2b8a031
2 changed files with 17 additions and 11 deletions
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5
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -38,8 +38,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
bool IsPostRAFlag,
LiveIntervals *lis)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
FirstDbgValue(0) {
assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) &&

23
lib/CodeGen/ScheduleDAGInstrs.h
View File

@ -171,16 +171,20 @@ namespace llvm {
const MachineFrameInfo *MFI;
const InstrItineraryData *InstrItins;
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
/// Live Intervals provides reaching defs in preRA scheduling.
LiveIntervals *LIS;
/// State specific to the current scheduling region.
///
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
// The block in which to insert instructions
/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
/// the def-side latency only.
bool UnitLatencies;
/// State specific to the current scheduling region.
/// ------------------------------------------------
/// The block in which to insert instructions
MachineBasicBlock *BB;
/// The beginning of the range to be scheduled.
@ -196,9 +200,8 @@ namespace llvm {
/// scheduling region is mapped to an SUnit.
DenseMap<MachineInstr*, SUnit*> MISUnitMap;
/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
/// the def-side latency only.
bool UnitLatencies;
/// State internal to DAG building.
/// -------------------------------
/// Defs, Uses - Remember where defs and uses of each register are as we
/// iterate upward through the instructions. This is allocated here instead
@ -220,6 +223,8 @@ namespace llvm {
LoopDependencies LoopRegs;
/// DbgValues - Remember instruction that preceeds DBG_VALUE.
/// These are generated by buildSchedGraph but persist so they can be
/// referenced when emitting the final schedule.
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector;
DbgValueVector DbgValues;