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[AMDGPU] Handle s_branch to another section.
Currently, if target of s_branch instruction is in another section, it will fail with the error of undefined label. Although in this case, the label is not undefined but present in another section. This patch tries to handle this issue. So while handling fixup_si_sopp_br fixup in getRelocType, if the target label is undefined we issue an error as before. If it is defined, a new relocation type R_AMDGPU_REL16 is returned. This issue has been reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100181 and https://bugs.llvm.org/show_bug.cgi?id=45887. Before https://reviews.llvm.org/D79943, we used to get an crash for this scenario. The crash is fixed now but the we still get an undefined label error. Jumps to other section can arise with hold/cold splitting. A patch to handle the relocation in lld will follow shortly. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D105760
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@ -1574,6 +1574,7 @@ The following relocation types are supported:
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``R_AMDGPU_REL32_HI`` Static 11 ``word32`` (S + A - P) >> 32
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*reserved* 12
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``R_AMDGPU_RELATIVE64`` Dynamic 13 ``word64`` B + A
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``R_AMDGPU_REL16`` Static 14 ``word16`` ((S + A - P) - 4) / 4
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========================== ======= ===== ========== ==============================
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``R_AMDGPU_ABS32_LO`` and ``R_AMDGPU_ABS32_HI`` are only supported by
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@ -15,3 +15,4 @@ ELF_RELOC(R_AMDGPU_GOTPCREL32_HI, 9)
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ELF_RELOC(R_AMDGPU_REL32_LO, 10)
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ELF_RELOC(R_AMDGPU_REL32_HI, 11)
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ELF_RELOC(R_AMDGPU_RELATIVE64, 13)
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ELF_RELOC(R_AMDGPU_REL16, 14)
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@ -80,9 +80,12 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
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const auto *SymA = Target.getSymA();
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assert(SymA);
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Ctx.reportError(Fixup.getLoc(),
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Twine("undefined label '") + SymA->getSymbol().getName() + "'");
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return ELF::R_AMDGPU_NONE;
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if (SymA->getSymbol().isUndefined()) {
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Ctx.reportError(Fixup.getLoc(), Twine("undefined label '") +
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SymA->getSymbol().getName() + "'");
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return ELF::R_AMDGPU_NONE;
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}
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return ELF::R_AMDGPU_REL16;
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}
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llvm_unreachable("unhandled relocation type");
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@ -9,6 +9,7 @@
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// CHECK: R_AMDGPU_GOTPCREL32_HI global_var2
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// CHECK: R_AMDGPU_REL32_LO global_var3
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// CHECK: R_AMDGPU_REL32_HI global_var4
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// CHECK: R_AMDGPU_REL16 .text.unlikely
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// CHECK: R_AMDGPU_ABS32 var
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// CHECK: }
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// CHECK: .rel.data {
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@ -25,6 +26,11 @@ kernel:
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s_mov_b32 s4, global_var2@gotpcrel32@hi
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s_mov_b32 s5, global_var3@rel32@lo
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s_mov_b32 s6, global_var4@rel32@hi
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s_branch cold
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.section .text.unlikely
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cold:
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s_add_i32 s15, s15, 1
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.globl global_var0
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.globl global_var1
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@ -18,6 +18,7 @@
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# CHECK-NEXT: 0x0 R_AMDGPU_REL32_LO - 0x0
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# CHECK-NEXT: 0x0 R_AMDGPU_REL32_HI - 0x0
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# CHECK-NEXT: 0x0 R_AMDGPU_RELATIVE64 - 0x0
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# CHECK-NEXT: 0x0 R_AMDGPU_REL16 - 0x0
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# CHECK-NEXT: }
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!ELF
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@ -43,3 +44,4 @@ Sections:
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- Type: R_AMDGPU_REL32_LO
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- Type: R_AMDGPU_REL32_HI
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- Type: R_AMDGPU_RELATIVE64
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- Type: R_AMDGPU_REL16
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