RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity

[VectorCombine] Limit scalarization to non-poison indices for now.

Browse Source 
As Eli mentioned post-commit in D103378, the result of the freeze may
still be out-of-range according to Alive2. So for now, just limit the
transform to indices that are non-poison.
This commit is contained in:
Florian Hahn 2021-06-14 16:38:27 +01:00
parent c92efb7d33
commit 5af9313d31
2 changed files with 13 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Transforms/Vectorize/VectorCombine.cpp
View File

@ -888,6 +888,9 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) {
if (!UI || UI->getParent() != LI->getParent())
return false;
if (!isGuaranteedNotToBePoison(UI->getOperand(1), &AC, LI, &DT))
return false;
// Check if any instruction between the load and the extract may modify
// memory.
if (LastCheckedInst->comesBefore(UI)) {
@ -928,9 +931,6 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) {
Builder.SetInsertPoint(EI);
Value *Idx = EI->getOperand(1);
if (!isGuaranteedNotToBePoison(Idx, &AC, LI, &DT))
Idx = Builder.CreateFreeze(Idx);
Value *GEP =
Builder.CreateInBoundsGEP(FixedVT, Ptr, {Builder.getInt32(0), Idx});
auto *NewLoad = cast<LoadInst>(Builder.CreateLoad(

27
test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
View File

@ -147,9 +147,8 @@ define i32 @load_extract_idx_var_i64_known_valid_by_and(<4 x i32>* %x, i64 %idx)
; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_and(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i64 [[IDX:%.*]], 3
; CHECK-NEXT: [[TMP0:%.*]] = freeze i64 [[IDX_CLAMPED]]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32>* [[X:%.*]], i32 0, i64 [[TMP0]]
; CHECK-NEXT: [[R:%.*]] = load i32, i32* [[TMP1]], align 4
; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i32> [[LV]], i64 [[IDX_CLAMPED]]
; CHECK-NEXT: ret i32 [[R]]
;
entry:
@ -193,9 +192,8 @@ define i32 @load_extract_idx_var_i64_known_valid_by_urem(<4 x i32>* %x, i64 %idx
; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_urem(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i64 [[IDX:%.*]], 4
; CHECK-NEXT: [[TMP0:%.*]] = freeze i64 [[IDX_CLAMPED]]
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32>* [[X:%.*]], i32 0, i64 [[TMP0]]
; CHECK-NEXT: [[R:%.*]] = load i32, i32* [[TMP1]], align 4
; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i32> [[LV]], i64 [[IDX_CLAMPED]]
; CHECK-NEXT: ret i32 [[R]]
;
entry:
@ -571,12 +569,9 @@ define i32 @load_multiple_extracts_with_variable_indices_large_vector_all_valid_
; CHECK-LABEL: @load_multiple_extracts_with_variable_indices_large_vector_all_valid_by_and(
; CHECK-NEXT: [[IDX_0_CLAMPED:%.*]] = and i64 [[IDX_0:%.*]], 15
; CHECK-NEXT: [[IDX_1_CLAMPED:%.*]] = and i64 [[IDX_1:%.*]], 15
; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[IDX_0_CLAMPED]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[X:%.*]], i32 0, i64 [[TMP1]]
; CHECK-NEXT: [[E_0:%.*]] = load i32, i32* [[TMP2]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = freeze i64 [[IDX_1_CLAMPED]]
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[X]], i32 0, i64 [[TMP3]]
; CHECK-NEXT: [[E_1:%.*]] = load i32, i32* [[TMP4]], align 4
; CHECK-NEXT: [[LV:%.*]] = load <16 x i32>, <16 x i32>* [[X:%.*]], align 64
; CHECK-NEXT: [[E_0:%.*]] = extractelement <16 x i32> [[LV]], i64 [[IDX_0_CLAMPED]]
; CHECK-NEXT: [[E_1:%.*]] = extractelement <16 x i32> [[LV]], i64 [[IDX_1_CLAMPED]]
; CHECK-NEXT: [[RES:%.*]] = add i32 [[E_0]], [[E_1]]
; CHECK-NEXT: ret i32 [[RES]]
;
@ -594,11 +589,9 @@ define i32 @load_multiple_extracts_with_variable_indices_large_vector_all_valid_
; CHECK-LABEL: @load_multiple_extracts_with_variable_indices_large_vector_all_valid_by_and_some_noundef(
; CHECK-NEXT: [[IDX_0_CLAMPED:%.*]] = and i64 [[IDX_0:%.*]], 15
; CHECK-NEXT: [[IDX_1_CLAMPED:%.*]] = and i64 [[IDX_1:%.*]], 15
; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[IDX_0_CLAMPED]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[X:%.*]], i32 0, i64 [[TMP1]]
; CHECK-NEXT: [[E_0:%.*]] = load i32, i32* [[TMP2]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[X]], i32 0, i64 [[IDX_1_CLAMPED]]
; CHECK-NEXT: [[E_1:%.*]] = load i32, i32* [[TMP3]], align 4
; CHECK-NEXT: [[LV:%.*]] = load <16 x i32>, <16 x i32>* [[X:%.*]], align 64
; CHECK-NEXT: [[E_0:%.*]] = extractelement <16 x i32> [[LV]], i64 [[IDX_0_CLAMPED]]
; CHECK-NEXT: [[E_1:%.*]] = extractelement <16 x i32> [[LV]], i64 [[IDX_1_CLAMPED]]
; CHECK-NEXT: [[RES:%.*]] = add i32 [[E_0]], [[E_1]]
; CHECK-NEXT: ret i32 [[RES]]
;